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8387d?avr?02/2013 features ? high-performance, low-power atmel ? avr ? xmega ? 8/16-bit microcontroller ? nonvolatile program and data memories ? 16k - 128kb of in-system self-programmable flash ? 4k - 8kb boot section ? 1k - 2kb eeprom ? 2k - 8kb internal sram ? peripheral features ? four-channel dma controller ? eight-channel event system ? five 16-bit timer/counters ? three timer/counters with 4 output compare or input capture channels ? two timer/counters with 2 output compare or input capture channels ? high-resolution extensions on all timer/counters ? advanced waveform extension (awex) on one timer/counter ? one usb device interface ? usb 2.0 full speed (12mbps) and low speed (1.5mbps) device compliant ? 32 endpoints with full configuration flexibility ? five usarts with irda support for one usart ? two two-wire interfaces with dual address match (i 2 c and smbus compatible) ? two serial peripheral interfaces (spis) ? aes and des crypto engine ? crc-16 (crc-ccitt) and crc-32 (ieee ? 802.3) generator ? 16-bit real time counter (rtc) with separate oscillator ? one twelve-channel, 12-bit, 2msps a nalog to digital converter ? one two-channel, 12-bit, 1msps digital to analog converter ? two analog comparators with window compare function, and current sources ? external interrupts on all general purpose i/o pins ? programmable watchdog timer with separate on-chip ultra low power oscillator ? qtouch ? library support ? capacitive touch buttons, sliders and wheels ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal and external clock op tions with pll and prescaler ? programmable multilevel interrupt controller ? five sleep modes ? programming and debug interfaces ? pdi (program and debug interface) ? i/o and packages ? 34 programmable i/o pins ? 44 - lead tqfp ? 44 - pad vqfn/qfn ? 49 - ball vfbga ? operating voltage ? 1.6 ? 3.6v ? operating frequency ? 0 ? 12mhz from 1.6v ? 0 ? 32mhz from 2.7v 8/16-bit atmel xmega microcontroller atxmega128a4u / atxmega64a4u* / atxmega32a4u / atxmega16a4u *preliminary
2 xmega a4u [datasheet] 8387d?avr?02/2013 1. ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering information. 2. pb-free packaging, complies to the european directive for restri ction of hazardous substances (rohs directive). also halide f ree and fully green. 3. for packaging information, see ?instruction set summary? on page 62 . 4. tape and reel typical applications ordering code flash (bytes) eeprom (bytes) sram (bytes) speed (mhz) power supply package (1)(2)(3) temp. atxmega128a4u-au 128k + 4k 2k 8k 32 1.6 - 3.6v 44a -40 ? c - 85 ? c atxmega128a4u-aur (4) 128k + 4k 2k 8k atxmega64a4u-au 64k + 4k 2k 4k atxmega64a4u-aur (4) 64k + 4k 2k 4k atxmega32a4u-au 32k + 4k 1k 4k atxmega32a4u-aur (4) 32k + 4k 1k 4k atxmega16a4u-au 16k + 4k 1k 2k atxmega16a4u-aur (4) 16k + 4k 1k 2k atxmega128a4u-mh 128k + 4k 2k 8k pw atxmega128a4u-mhr (4) 128k + 4k 2k 8k atxmega64a4u-mh 64k + 4k 2k 4k atxmega64a4u-mhr (4) 64k + 4k 2k 4k atxmega32a4u-mh 32k + 4k 1k 4k 44m1 atxmega32a4u-mhr (4) 32k + 4k 1k 4k atxmega16a4u-mh 16k + 4k 1k 2k atxmega16a4u-mhr (4) 16k + 4k 1k 2k atxmega128a4u-cu 128k + 8k 2k 8k 49c2 atxmega128a4u-cur (4) 128k + 8k 2k 8k atxmega64a4u-cu 64k + 4k 2k 4k atxmega64a4u-cur (4) 64k + 4k 2k 4k atxmega32a4u-cu 32k + 4k 1k 4k atxmega32a4u-cur (4) 32k + 4k 1k 4k atxmega16a4u-cu 16k + 4k 1k 2k atxmega16a4u-cur (4) 16k + 4k 1k 2k package type 44a 44-lead, 10 x 10mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (tqfp) 44m1 44-pad, 7x7x1mm body, lead pitch 0.50mm, 5.20mm exposed pad, the rmally enhanced plastic very thin quad no lead package (vqfn) pw 44-pad, 7x7x1mm body, lead pitch 0.50mm, 5.20mm exposed pad, the rmally enhanced plastic very thin quad no lead package (vqfn) 49c2 49-ball (7 x 7 array), 0.65mm pitch, 5.0 x 5.0 x 1.0mm, very thin, fine-pitch ball grid array package (vfbga) industrial control climate control low power battery applications factory automation rf and zigbee ? power tools building control usb connectivity hvac board control sensor control utility metering white goods optical medical applications
3 xmega a4u [datasheet] 8387d?avr?02/2013 2. pinout/block diagram figure 2-1. block diagram and qfn/tqfp pinout note: 1. for full details on pinout and pin functions refer to ?pinout and pin functions? on page 55 . 1 2 3 4 44 43 42 41 40 39 38 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 pa0 pa1 pa2 pa3 pa4 pb0 pb1 pb3 pb2 pa7 pa6 pa5 gnd vcc pc0 vcc gnd pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 vcc gnd pd7 pe0 pe1 pe2 pe3 reset/pdi pdi pr0 pr1 avcc gnd power supervision port a event routing network dma controller bus matrix sram flash adc ac0:1 ocd port e port d prog/debug interface eeprom port c tc0:1 event system controller watchdog timer watchdog osc/clk control real time counter interrupt controller data bus data bus port r usart0:1 twi spi tc0:1 usart0:1 spi tc0 usart0 twi port b dac aref aref sleep controller reset controller ircom crypto / crc usb cpu internal references internal oscillators xosc tosc digital function analog function / oscillators programming, debug, test external clock / crystal pins general purpose i /o ground power
4 xmega a4u [datasheet] 8387d?avr?02/2013 figure 2-2. bga pinout table 2-1. bga pinout 1 2 3 4 5 6 7 a pa3 avcc gnd pr1 pr0 pdi_data pe3 b pa4 pa1 pa0 gnd reset/ pdi_clk pe2 vcc c pa5 pa2 pa6 pa7 gnd pe1 gnd d pb1 pb2 pb3 pb0 gnd pd7 pe0 e gnd gnd pc3 gnd pd4 pd5 pd6 f vcc pc0 pc4 pc6 pd0 pd1 pd3 g pc1 pc2 pc5 pc7 gnd vcc pd2 a b c d e f g 1 234567 a b c d e f g 765432 1 top view bottom view
5 xmega a4u [datasheet] 8387d?avr?02/2013 3. overview the atmel avr xmega is a family of low power, high perfo rmance, and peripheral rich 8/16-bit microcontrollers based on the avr enhanced risc architecture. by executing instructions in a single clock cycle, the avr xmega devices achieve cpu throughput approaching one million instructions per second (mips) per megahertz, allowing the system designer to optimize power consumption versus processing speed. the avr cpu combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumu lator or cisc based microcontrollers. the avr xmega a4u devices provide the following featur es: in-system programmable flash with read-while-write capabilities; internal eeprom and sram; four-channel dma controller, eight-channel event system and programmable multilevel interrupt controller, 34 general purpose i/o lines , 16-bit real-time counter (r tc); five flexible, 16-bit timer/counters with compare and pwm channels; five usarts; two two-wire serial interfaces (twis); one full speed usb 2.0 interface; two serial peripheral interfaces (spis); aes and des cryptographic engine; one twelve-channel, 12- bit adc with programmable gain; one 2-channel 12-bit da c; two analog comparators (acs) with window mode; programmable watchdog timer with separate internal oscillator ; accurate internal oscillators with pll and prescaler; and programmable brown-out detection. the program and debug interface (pdi), a fast, two-pi n interface for programming and debugging, is available. the atx devices have five software selectable power saving modes. the idle mode stops the cpu while allowing the sram, dma controller, event system, interrupt controller, and all peripherals to continue functioning. the power-down mode saves the sram and register contents, but stops the osc illators, disabling all other functions until the next twi, usb resume, or pin-change interrupt, or reset. in power-sav e mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. in standby mode, the external crystal oscillator keeps running while the rest of t he device is sleeping. this allows very fast startup from the external crystal, combined with low power consumption. in extended standby mode, both the main oscillator and the asynchronous timer continue to run. to further reduce pow er consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. atmel offers a free qtouch library for embedding capacitive touch buttons, sliders and wheels functionality into avr microcontrollers. the devices are manufactured using atmel high-density, nonvol atile memory technology. the program flash memory can be reprogrammed in-system through the pdi. a boot loader runni ng in the device can use any interface to download the application program to the flash memory. the boot loader softwar e in the boot flash section will continue to run while the application flash section is updated, providing true read-while-w rite operation. by combining an 8/16-bit risc cpu with in-system, self-programmable flash, the avr xmega is a powerfu l microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. all atmel avr xmega devices are supported with a full suite of program and system development tools, including c compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
6 xmega a4u [datasheet] 8387d?avr?02/2013 3.1 block diagram figure 3-1. xmega a4u block diagram power supervision por/bod & reset port a (8) port b (8) dma controller sram adca aca dacb ocd int. refs. pdi pa[0..7] pb[0..7] watchdog timer watchdog oscillator interrupt controller data bus prog/debug controller vcc gnd oscillator circuits/ clock generation oscillator control real time counter event system controller arefa arefb pdi_data reset/ pdi_clk sleep controller des crc port c (8) pc[0..7] tcc0:1 usartc0:1 twic spic pd[0..7] pe[0..3] port d (8) tcd0:1 usartd0:1 spid tce0 usarte0 twie port e (4) tempref aes usb port r (2) data bus nvm controller m o r p e e h s a l f ircom bus matrix cpu event routing network xtal1/ tosc1 xtal2/ tosc2 pr[0..1] tosc1 (optional) tosc2 (optional) digital function analog function programming, debug, test oscillator/crystal/cloc k general purpose i/o
7 xmega a4u [datasheet] 8387d?avr?02/2013 4. resources a comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr . 4.1 recommended reading ? atmel avr xmega au manual ? xmega application notes this device data sheet only contains part specific informati on with a short description of each peripheral and module. the xmega au manual describes the modules and peripherals in depth. the xmega application notes contain example code and show applied use of the modules and peripherals. all documentation are available from www.atmel.com/avr .
8 xmega a4u [datasheet] 8387d?avr?02/2013 5. capacitive touch sensing the atmel qtouch library provides a simple to use soluti on to realize touch sensitive interfaces on most atmel avr microcontrollers. the patented charge-transfer signal acqui sition offers robust sensing and includes fully debounced reporting of touch keys and includes adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the qtouch library includes support for the qtouch and qmatrix acquisition methods. touch sensing can be added to any application by linki ng the appropriate atmel qtouch library for the avr microcontroller. this is done by using a simple set of apis to define the touch channels and sensors, and then calling the touch sensing api?s to retrieve the channel information and determine the touch sensor states. the qtouch library is free and downloadable from the atmel website at the following location: www.atmel.com/qtouchlibrary . for implementation details and other information, refer to the qtouch library user guide - also available for download from the atmel website.
9 xmega a4u [datasheet] 8387d?avr?02/2013 6. avr cpu 6.1 features ? 8/16-bit, high-performance atmel avr risc cpu ? 142 instructions ? hardware multiplier ? 32x8-bit registers directly connected to the alu ? stack in ram ? stack pointer accessible in i/o memory space ? direct addressing of up to 16mb of program memory and 16mb of data memory ? true 16/24-bit access to 16/24-bit i/o registers ? efficient support for 8-, 16-, and 32-bit arithmetic ? configuration change protection of system-critical features 6.2 overview all atmel avr xmega devices use the 8/16-bit avr cpu. t he main function of the cpu is to execute the code and perform all calculations. the cpu is able to access memories , perform calculations, control peripherals, and execute the program in the flash memory. interrupt handling is described in a separate section, refer to ?interrupts and programmable multilevel interrupt controller? on page 28 . 6.3 architectural overview in order to maximize performance and parallelism, the avr cpu uses a harvard architecture with separate memories and buses for program and data. instructions in the program memo ry are executed with single-level pipelining. while one instruction is being executed, the next instruction is pre-fe tched from the program memory. this enables instructions to be executed on every clock cycle. for details of all avr instructions, refer to http://www.atmel.com/avr . figure 6-1. block diagram of the avr cpu architecture. the arithmetic logic unit (alu) supports arithmetic and l ogic operations between registers or between a constant and a register. single-register operations can also be executed in t he alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation.
10 xmega a4u [datasheet] 8387d?avr?02/2013 the alu is directly connected to the fast-access register file. the 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmet ic logic unit (alu) operation between registers or between a register and an immediate. six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations. the memory spaces are linear. the data memory space and the program memory space are two different memory spaces. the data memory space is divided into i/o registers, sram, and external ram. in addition, the eeprom can be memory mapped in the data memory. all i/o status and control registers reside in the lowest 4kb addresses of the data memory. this is referred to as the i/o memory space. the lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3f. the rest is the extended i/o memory space, ranging from 0x0040 to 0x0fff. i/o registers here must be accessed as data space locations using load (ld/lds/ldd) and store (st/sts/std) instructions. the sram holds data. code execution from sram is not s upported. it can easily be accessed through the five different addressing modes supported in the avr architecture. the first sram address is 0x2000. data addresses 0x1000 to 0x1fff are reserved for memory mapping of eeprom. the program memory is divided in two sections, the applic ation program section and the boot program section. both sections have dedicated lock bits for write and read/write protection. the spm instruction that is used for self- programming of the application flash memory must reside in t he boot program section. the application section contains an application table section with separate lock bits for write and read/write protection. the application table section can be used for safe storing of nonvolatile data in the program memory. 6.4 alu - arithmetic logic unit the arithmetic logic unit (alu) supports arithmetic and l ogic operations between registers or between a constant and a register. single-register operations can also be executed. the alu operates in direct connection with all 32 general purpose registers. in a single clock cycle, arithmetic oper ations between general purpose registers or between a register and an immediate are executed and the result is stored in the r egister file. after an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. alu operations are divided into three main categories ? ar ithmetic, logical, and bit functions. both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32- bit aritmetic. the hardware multiplier supports signed and unsigned multiplication and fractional format. 6.4.1 hardware multiplier the multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. the hardware multiplier supports different variations of signed and unsigned integer and fractional numbers: ? multiplication of unsigned integers ? multiplication of signed integers ? multiplication of a signed integer with an unsigned integer ? multiplication of unsigned fractional numbers ? multiplication of signed fractional numbers ? multiplication of a signed fractional number with an unsigned one a multiplication takes two cpu clock cycles. 6.5 program flow after reset, the cpu starts to execute instructions from the lowest address in the flash programmemory ?0.? the program counter (pc) addresses the next instruction to be fetched.
11 xmega a4u [datasheet] 8387d?avr?02/2013 program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. most avr instructions use a 16-bit word format, while a limited number use a 32-bit format. during interrupts and subroutine calls, the return address pc is stored on the stack. the stack is allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. after reset, the stack pointer (sp) points to the highest address in the internal sram. the sp is read/write accessible in the i/o memory space, enabling easy implementation of multiple stacks or stack areas. the data sram can easily be accessed through the five different addressing modes supported in the avr cpu. 6.6 status register the status register (sreg) contains information about the result of the most recently executed arithmetic or logic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specif ied in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when ente ring an interrupt routine nor restored when returning from an interrupt. this must be handled by software. the status register is accessible in the i/o memory space. 6.7 stack and stack pointer the stack is used for storing return addresses after interrupts and subroutine calls. it can also be used for storing temporary data. the stack pointer (sp) register always points to the top of the stack. it is implemented as two 8-bit registers that are accessible in the i/o memory space. data are pushed and popped from the stack using the push and pop instructions. the stack grows from a higher memory locati on to a lower memory location. this implies that pushing data onto the stack decreases the sp, and popping data off the stack increases the sp. the sp is automatically loaded after reset, and the initial value is the highest address of the internal sram. if the sp is changed, it must be set to point above address 0x2000, and it must be defined before any subr outine calls are executed or before interrupts are enabled. during interrupts or subroutine calls, the return address is automatically pushed on the stack. the return address can be two or three bytes, depending on program memory size of the device. for devices with 128kb or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. for devices with more than 128kb of program memory, the return address is three bytes, and hence the sp is decremented/incremented by three. the return address is popped off the stack when returning from interrupts using the reti instruction, and from subroutine calls using the ret instruction. the sp is decremented by one when data are pushed on the stack with the push instruction, and incremented by one when data is popped off the stack using the pop instruction. to prevent corruption when updating the stack pointer from software, a write to spl will automatically disable interrupts for up to four instructions or until the next i/o memory write. after reset the stack pointer is initialized to the highest address of the sram. see figure 7-3 on page 15 . 6.8 register file the register file consists of 32 x 8-bit general purpose worki ng registers with single clock cycle access time. the register file supports the following input/output schemes: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input six of the 32 registers can be used as three 16-bit address r egister pointers for data space addressing, enabling efficient address calculations. one of these address pointers can also be used as an address pointer for lookup tables in flash program memory.
12 xmega a4u [datasheet] 8387d?avr?02/2013 7. memories 7.1 features ? flash program memory ? one linear address space ? in-system programmable ? self-programming and boot loader support ? application section for application code ? application table section for application code or data storage ? boot section for application code or boot loader code ? separate read/write protectio n lock bits for all sections ? built in fast crc check of a selectable flash program memory section ? data memory ? one linear address space ? single-cycle access from cpu ? sram ? eeprom byte and page accessible optional memory mapping fo r direct load and store ? i/o memory configuration and status registers for all peripherals and modules 16 bit-accessible general purpose registers for global variables or flags ? bus arbitration deterministic priority handling between cpu, dma controller, and other bus masters ? separate buses for sram, eeprom and i/o memory simultaneous bus access for cpu and dma controller ? production signature row memory for factory programmed data ? id for each microcontroller device type ? serial number for each device ? calibration bytes for factory calibrated peripherals ? user signature row ? one flash page in size ? can be read and written from software ? content is kept after chip erase 7.2 overview the atmel avr architecture has two main memory spaces, the program memory and the data memory. executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. the data memory includes the internal sram, and eeprom for nonvol atile data storage. all memory spaces are linear and require no memory bank switching. nonvolatile memory (n vm) spaces can be locked for further write and read/write operations. this prevents unrestricted access to the application software. a separate memory section contains the fuse bytes. these are used for configuring important system functions, and can only be written by an external programmer. the available memory size configurations are shown in ?ordering information? on page 2 . in addition, each device has a flash memory signature row for calibration data, device identification, serial number etc.
13 xmega a4u [datasheet] 8387d?avr?02/2013 7.3 flash program memory the atmel avr xmega devices contain on-chip, in-system reprogrammable flash memory for program storage. the flash memory can be accessed for read and write from an ex ternal programmer through the pdi or from application software running in the device. all avr cpu instructions are 16 or 32 bits wide, and each flas h location is 16 bits wide. the flash memory is organized in two main sections, the application section and the boot loader section. the sizes of the different sections are fixed, but device-dependent. these two sections have separate lock bits, and can have different levels of protection. the store program memory (spm) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section. the application section contains an application table section with separate lock settings. this enables safe storage of nonvolatile data in the program memory. figure 7-1. flash program memory (hexadecimal address). 7.3.1 application section the application section is the section of the flash that is used for storing the executable application code. the protection level for the application section can be selected by the boot lock bits for this section. the application section can not store any boot loader code since the spm instruction cannot be executed from the application section. 7.3.2 application table section the application table section is a part of the application sect ion of the flash memory that can be used for storing data. the size is identical to the boot loader section. the protection level for the application table section can be selected by the boot lock bits for this section. the possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. if this section is not used for data, application code can reside here. 7.3.3 boot loader section while the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the spm instruction can only initiate programming when executing fr om this section. the spm instruction can access the entire flash, including the boot lo ader section itself. the protection level for the boot loader section can be selected by the boot loader lock bits. if this section is not used for boot loader software, application code can be stored here. word address atxmega128a4u atxmega64a4u atxmega32a4u atxmega16a4u 0000 application section (128k/64k/32k/16k) ... efff / 77ff / 37ff / 17ff f000 / 7800 / 3800 / 1800 application table section (4k/4k/4k/4k) ffff / 7fff / 3fff / 1fff 10000 / 8000 / 4000 / 2000 boot section (8k/4k/4k/4k) 10fff / 87ff / 47ff / 27ff
14 xmega a4u [datasheet] 8387d?avr?02/2013 7.3.4 production signature row the production signature row is a separate memory section for factory programmed data. it contains calibration data for functions such as oscillators and analog modules. some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. other va lues must be loaded from the signature row and written to the corresponding peripheral registers from software . for details on calibration conditions, refer to ?electrical characteristics? on page 71 . the production signature row also contains an id that identif ies each microcontroller device type and a serial number for each manufactured device. the serial number consists of the production lot number, wafer number, and wafer coordinates for the device. the device id for the available devices is shown in table 7-2 . the production signature row cannot be written or erased, but it can be read from application software and external programmers. figure 7-2. device id bytes fo r atmel avr xmega a4u devices. 7.3.5 user signature row the user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. it is one flash page in size, and is mean t for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. this section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. this ensures parameter storage during multiple program/erase operations and on-chip debug sessions. 7.4 fuses and lock bits the fuses are used to configure important system functions , and can only be written from an external programmer. the application software can read the fuses. the fuses are used to configure reset sources such as brownout detector and watchdog, startup configuration, jtag enable, and jtag user id. the lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should b e blocked). lock bits can be written by external programmers and application software, but only to stricter protection levels. chip erase is the only way to erase the lock bits. to ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased. an unprogrammed fuse or lock bit will have the value one, whil e a programmed fuse or lock bit will have the value zero. both fuses and lock bits are reprogrammable like the flash program memory. 7.5 data memory the data memory contains the i/o memory, internal sram , optionally memory mapped eeprom, and external memory if available. the data memory is organized as one continuous memory section, see figure 7-3 . to simplify development, i/o memory, eeprom and sram will always have the same start addresses for all atmel avr xmega devices. device device id bytes byte 2 byte 1 byte 0 atxmega16a4u 41 94 1e atxmega32a4u 41 95 1e atxmega64a4u 46 96 1e atxmega128a4u 46 97 1e
15 xmega a4u [datasheet] 8387d?avr?02/2013 figure 7-3. data memory map (hexadecimal address). 7.6 eeprom all devices have eeprom for nonvolatile data storage. it is either addressable in a separate data space (default) or memory mapped and accessed in normal data space. the eeprom supports both byte and page access. memory mapped eeprom allows highly efficient eeprom readi ng and eeprom buffer loading. when doing this, eeprom is accessible using load and store instructions. memory mapped eeprom will always start at hexadecimal address 0x1000. 7.7 i/o memory the status and configuration registers for peripherals and modules, including the cpu, are addressable through i/o memory locations. all i/o locations can be accessed by the load (ld/lds/ldd) and store (st/sts/std) instructions, which are used to transfer data between the 32 registers in the register file and the i/o memory. the in and out instructions can address i/o memory locations in the range of 0x00 to 0x3f directly. in the address range 0x00 - 0x1f, single-cycle instructions for manipulation and c hecking of individual bits are available. the i/o memory address for all peripherals and modules in xmega a4u is shown in the ?peripheral module address map? on page 60 . 7.7.1 general purpose i/o registers the lowest 16 i/o memory addresses are reserved as general purpose i/o registers. these registers can be used for storing global variables and flags, as they are directly bit- accessible using the sbi, cbi, sbis, and sbic instructions. byte address atxmega64a4u byte address atxmega32a4u byte address atxmega16a4u 0 i/o registers (4k) 0 i/o registers (4k) 0 i/o registers (4k) fff fff fff 1000 eeprom (2k) 1000 eeprom (1k) 1000 eeprom (1k) 17ff 13ff 13ff reserved reserved reserved 2000 internal sram (4k) 2000 internal sram (4k) 2000 internal sram (2k) 2fff 2fff 27ff byte address atxmega128a4u 0 i/o registers (4k) fff 1000 eeprom (2k) 17ff reserved 2000 internal sram (8k) 3fff
16 xmega a4u [datasheet] 8387d?avr?02/2013 7.8 data memory and bus arbitration since the data memory is organized as four separate sets of memories, the different bus masters (cpu, dma controller read and dma controller write, etc.) can access different memory sections at the same time. 7.9 memory timing read and write access to the i/o memory takes one cpu clock cycle. a write to sram takes one cycle, and a read from sram takes two cycles. for burst read (dma), new data are available every cycle. eeprom page load (write) takes one cycle, and three cycles are required for read. for burst read, new data are available every second cycle. refer to the instruction summary for more details on instructions and instruction timing. 7.10 device id and revision each device has a three-byte device id. this id identifies atmel as the manufacturer of the device and the device type. a separate register contains the revision number of the device. 7.11 i/o memory protection some features in the device are regarded as critical for safety in some applications. due to this, it is possible to lock the i/o register related to the clock system, the event system, and the advanced waveform extensions. as long as the lock is enabled, all related i/o registers are locked and they can not be written from the application software. the lock registers themselves are protected by the configuration change protection mechanism. 7.12 flash and eeprom page size the flash program memory and eeprom data memory are or ganized in pages. the pages are word accessible for the flash and byte accessible for the eeprom. table 7-1 on page 16 shows the flash program memory organization and program counter (pc) size. flash write and erase operations are performed on one page at a time, while reading the flash is done one byte at a time. for flash access the z-pointer (z[m:n]) is used for addressing. the mo st significant bits in the address (fpage) give the page number and the least significant address bits (fword) give the word in the page. table 7-1. number of words and pages in the flash. table 7-2 shows eeprom memory organization for the atme l avr xmega a4u devices. eeeprom write and erase operations can be performed one page or one byte at a time, while reading the eeprom is done one byte at a time. for eeprom access the nvm address register (addr[m:n]) is used for addressing. the most significant bits in the address (e2page) give the page number and the least significant address bits (e2byte) give the byte in the page. devices pc size flash size page size fword fpage application boot bits bytes words size no of pages size no of pages atxmega16a4u 14 16k + 4k 128 z[6:0] z[13:7] 16k 64 4k 16 atxmega32a4u 15 32k + 4k 128 z[6:0] z[14:7] 32k 128 4k 16 atxmega64a4u 16 64k + 4k 128 z[6:0] z[15:7] 64k 256 4k 16 atxmega128a4u 17 128k + 8k 256 z[8:0] z[16:7] 128k 512 8k 32
17 xmega a4u [datasheet] 8387d?avr?02/2013 table 7-2. number of byte s and pages in the eeprom. devices eeprom page size e2byte e2page no of pages size bytes atxmega16a4u 1k 32 addr[4:0] addr[10:5] 32 atxmega32a4u 1k 32 addr[4:0] addr[10:5] 32 atxmega64a4u 2k 32 addr[4:0] addr[10:5] 64 atxmega128a4u 2k 32 addr[4:0] addr[10:5] 64
18 xmega a4u [datasheet] 8387d?avr?02/2013 8. dmac ? direct memory access controller 8.1 features ? allows high speed data transfers with minimal cpu intervention ? from data memory to data memory ? from data memory to peripheral ? from peripheral to data memory ? from peripheral to peripheral ? four dma channels with separate ? transfer triggers ? interrupt vectors ? addressing modes ? programmable channel priority ? from 1 byte to 16mb of data in a single transaction ? up to 64kb block transfers with repeat ? 1, 2, 4, or 8 byte burst transfers ? multiple addressing modes ?static ?incremental ? decremental ? optional reload of source and destination addresses at the end of each ?burst ?block ? transaction ? optional interrupt on end of transaction ? optional conn ection to crc generator for crc on dma data 8.2 overview the four-channel direct memory access (dma) controller can transfer data between memories and peripherals, and thus offload these tasks from the cpu. it enables high data transfer rates with minimum cpu intervention, and frees up cpu time. the four dma channels enable up to four independent and parallel transfers. the dma controller can move data between sram and peripherals, between sram locations and directly between peripheral registers. with access to all peripherals, the dma controller can handle automatic transfer of data to/from communication modules. the dma controller can also read from memory mapped eeprom. data transfers are done in continuous bursts of 1, 2, 4, or 8 by tes. they build block transfers of configurable size from 1 byte to 64kb. a repeat counter can be used to repeat each bl ock transfer for single transactions up to 16mb. source and destination addressing can be static, incremental or decre mental. automatic reload of source and/or destination addresses can be done after each burst or block transfer, or when a transaction is complete. application software, peripherals, and events can trigger dma transfers. the four dma channels have individual configuration and c ontrol settings. this include source, destination, transfer triggers, and transaction sizes. they have individual in terrupt settings. interrupt requests can be generated when a transaction is complete or when the dma controller detects an error on a dma channel. to allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished, and vice versa.
19 xmega a4u [datasheet] 8387d?avr?02/2013 9. event system 9.1 features ? system for direct peripheral-to-peripheral communication and signaling ? peripherals can directly send, receiv e, and react to peripheral events ? cpu and dma controller independent operation ? 100% predictable signal timing ? short and guaranteed response time ? eight event channels for up to eight different and parallel signal routing configurations ? events can be sent and/or used by most peripherals, clock system, and software ? additional func tions include ? quadrature decoders ? digital filtering of i/o pin state ? works in active mode and idle sleep mode 9.2 overview the event system enables direct peripheral-to-peripheral communication and signaling. it allows a change in one peripheral?s state to automatically trigger actions in other peripherals. it is designed to provide a predictable system for short and predictable response times between peripherals. it allows for autonomous peripheral control and interaction without the use of interrupts, cpu, or dma controller resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. it also allows for synchronized timing of actions in several peripheral modules. a change in a peripheral?s state is referred to as an event, and usually corresponds to the peripheral?s interrupt conditions. events can be directly passed to other peripherals using a dedicated routing network called the event routing network. how events are routed and used by the peripherals is configured in software. figure 9-1 on page 19 shows a basic diagram of all connected peripherals. the event system can directly connect together analog and digital converters, analog comparators, i/o port pins, the real-time counter, timer/counters, ir communication module (ircom), and usb interface. it can also be used to trigger dma trans actions (dma controller). events can also be generated from software and the peripheral clock. figure 9-1. event system overvi ew and connected peripherals. the event routing network consists of eight software-configurable multiplexers that control how events are routed and used. these are called event channels, and allow for up to eight parallel event routing configurations. the maximum routing latency is two peripheral clock cycles. the event system works in both active mode and idle sleep mode. dac timer / counters usb adc real time counter port pins cpu / software dma controller ircom event routing network event system controller clk per prescaler ac
20 xmega a4u [datasheet] 8387d?avr?02/2013 10. system clock and clock options 10.1 features ? fast start-up time ? safe run-time clock switching ? internal oscillators: ? 32mhz run-time calibrated and tuneable oscillator ? 2mhz run-time cal ibrated oscillator ? 32.768khz calibrated oscillator ? 32khz ultra low power (ulp) oscillator with 1khz output ? external clock options ? 0.4mhz - 16mhz crystal oscillator ? 32.768khz crystal oscillator ? external clock ? pll with 20mhz - 128m hz output frequency ? internal and external clock options and 1x to 31x multiplication ? lock detector ? clock prescalers with 1x to 2048x division ? fast peripheral clocks running at two and four times the cpu clock ? automatic run-time calibration of internal oscillators ? external oscillator and pll lo ck failure detection with op tional non-maskable interrupt 10.2 overview atmel avr xmega a4u devices have a flexible clock system supporting a large number of clock sources. it incorporates both accurate internal oscillators and ex ternal crystal oscillator and resonator support. a high-frequency phase locked loop (pll) and clock prescalers can be used to generate a wide range of clock frequencies. a calibration feature (dfll) is available, and can be used for automatic r un-time calibration of the internal oscillators to remove frequency drift over voltage and temperature. an oscillat or failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal oscillator if the external oscillator or pll fails. when a reset occurs, all clock sources except the 32khz ultra low power oscillator are disabled. after reset, the device will always start up running from the 2mhz internal oscill ator. during normal operation, the system clock source and prescalers can be changed from software at any time. figure 10-1 on page 21 presents the principal clock system in the xmega a4u family of devices. not all of the clocks need to be active at a given time. the clocks for the cpu and peripherals can be stopped using sleep modes and power reduction registers, as described in ?power management and sleep modes? on page 23 .
21 xmega a4u [datasheet] 8387d?avr?02/2013 figure 10-1. the clock system, clo ck sources and clock distribution. 10.3 clock sources the clock sources are divided in two main groups: internal oscillators and external clock sources. most of the clock sources can be directly enabled and disabled from softwa re, while others are automatically enabled or disabled, depending on peripheral settings. after reset, the device starts up running from the 2mhz internal oscillator. the other clock sources, dflls and pll, are turned off by default. the internal oscillators do not require any external component s to run. for details on characteristics and accuracy of the internal oscillators, refer to the device datasheet. 10.3.1 32khz ultra low power internal oscillator this oscillator provides an approximate 32khz clock. the 32khz ultra low power (ulp) internal oscillator is a very low power clock source, and it is not designed for high accuracy. the oscillator employs a built-in prescaler that provides a real time counter peripherals ram avr cpu non-volatile memory watchdog timer brown-out detector system clock prescalers usb prescaler system clock multiplexer (sclksel) pllsrc rtcsrc div32 32 khz int. ulp 32.768 khz int. osc 32.768 khz tosc 2 mhz int. osc 32 mhz int. osc 0.4 ? 16 mhz xtal div32 div32 div4 xoscsel pll usbsrc tosc1 tosc2 xtal1 xtal2 clk sys clk rtc clk per2 clk per clk cpu clk per4 clk usb
22 xmega a4u [datasheet] 8387d?avr?02/2013 1khz output. the oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. this oscillator can be selected as the clock source for the rtc. 10.3.2 32.768khz calibrate d internal oscillator this oscillator provides an approximate 32.768khz clock. it is calibrated during production to provide a default frequency close to its nominal frequency. the calibration register can also be written from software for run-time calibration of the oscillator frequency. the oscillator employs a built-in pre scaler, which provides both a 32.768khz output and a 1.024khz output. 10.3.3 32.768khz crystal oscillator a 32.768khz crystal oscillator can be connected between the tosc1 and tosc2 pins and enables a dedicated low frequency oscillator input circuit. a low power mode with reduc ed voltage swing on tosc2 is available. this oscillator can be used as a clock source for the system clock and rtc, and as the dfll reference clock. 10.3.4 0.4 - 16mhz crystal oscillator this oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16mhz. 10.3.5 2mhz run-time calibr ated internal oscillator the 2mhz run-time calibrated internal oscillator is the default system clock source after reset. it is calibrated during production to provide a default frequency close to its nominal frequency. a dfll can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. 10.3.6 32mhz run-time calib rated internal oscillator the 32mhz run-time calibrated internal oscillator is a high-frequency oscillator. it is calibrated during production to provide a default frequency close to its nominal frequency. a digital frequency looked loop (dfll) can be enabled for automatic run-time calibration of the oscillator to compens ate for temperature and voltage drift and optimize the oscillator accuracy. this oscillator can also be adjusted and calibrated to any frequency between 30mhz and 55mhz. the production signature row contains 48mhz calibration values intended used when the oscillator is used a full-speed usb clock source. 10.3.7 external clock sources the xtal1 and xtal2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator. xtal1 can be used as input for an external clock signal . the tosc1 and tosc2 pins is dedicated to driving a 32.768khz crystal oscillator. 10.3.8 pll with 1x-31x multiplication factor the built-in phase locked loop (pll) can be used to generat e a high-frequency system clock. the pll has a user- selectable multiplication factor of from 1 to 31. in combin ation with the prescalers, this gives a wide range of output frequencies from all clock sources.
23 xmega a4u [datasheet] 8387d?avr?02/2013 11. power management and sleep modes 11.1 features ? power management for adjusting power consumption and functions ? five sleep modes ?idle ? power down ? power save ? standby ? extended standby ? power reduction register to disable clock and turn off unused peripherals in active and idle modes 11.2 overview various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. this enables the atmel avr xmega microcontroller to stop unused modules to save power. all sleep modes are available and can be entered from active mode. in active mode, the cpu is executing application code. when the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. the application code decides which sleep m ode to enter and when. interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode. in addition, power reduction registers provide a method to st op the clock to individual peripherals from software. when this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. this reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone. 11.3 sleep modes sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. xmega microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution. a dedicated sleep instruction (sleep) is avail able to enter sleep mode. interrupts are used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. when an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from the first instruction after the sleep instruction. if other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. after wake-up, the cpu is halted for four cycles before execution starts. the content of the register file, sram and registers are kept during sleep. if a reset occurs during sleep, the device will reset, start up, and execute from the reset vector. 11.3.1 idle mode in idle mode the cpu and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller, event system and dma controller are kept running. any enabled interrupt will wake the device. 11.3.2 power-down mode in power-down mode, all clocks, including the real-time count er clock source, are stopped. this allows operation only of asynchronous modules that do not require a running clock. the only interrupts that can wake up the mcu are the two- wire interface address match interrupt, asynchronous port interrupts, and the usb resume interrupt.
24 xmega a4u [datasheet] 8387d?avr?02/2013 11.3.3 power-save mode power-save mode is identical to power down, with one excepti on. if the real-time counter (rtc) is enabled, it will keep running during sleep, and the device can also wake up from either an rtc overflow or compare match interrupt. 11.3.4 standby mode standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the cpu, peripheral, and rtc clocks are stopped. this reduces the wake-up time. 11.3.5 extended standby mode extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the cpu and peripheral clocks are stopped. this reduces the wake-up time.
25 xmega a4u [datasheet] 8387d?avr?02/2013 12. system control and reset 12.1 features ? reset the microcontroller and set it to initial state when a reset source goes active ? multiple reset sources that cover different situations ? power-on reset ? external reset ? watchdog reset ? brownout reset ? pdi reset ? software reset ? asynchronous operation ? no running system clock in the device is required for reset ? reset status register for reading the reset source from the application code 12.2 overview the reset system issues a microcontroller reset and sets the device to its initial state. this is for situations where operation should not start or continue, such as when the micr ocontroller operates below its power supply rating. if a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. the i/o pins are immediately tri-stated. the program counter is set to the reset vector location, and all i/o registers are set to their initial values. the sram content is kept. however, if the device accesses the sram when a reset occurs, the content of the accessed location can not be guaranteed. after reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. by default, this is the lowest program memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section. the reset functionality is asynchronous, and so no running syst em clock is required to reset the device. the software reset feature makes it possible to issue a controlled system reset from the user software. the reset status register has individual status flags fo r each reset source. it is cleared at power-on reset, and shows which sources have issued a reset since the last power-on. 12.3 reset sequence a reset request from any reset source will immediately rese t the device and keep it in reset as long as the request is active. when all reset requests are released, the device will go through three stages before the device starts running again: ? reset counter delay ? oscillator startup ? oscillator calibration if another reset requests occurs during this process, the reset sequence will start over again. 12.4 reset sources 12.4.1 power-on reset a power-on reset (por) is generated by an on-chip detection circuit. the por is activated when the v cc rises and reaches the por threshold voltage (v pot ), and this will start the reset sequence. the por is also activated to power down the device properly when the v cc falls and drops below the v pot level. the v pot level is higher for falling v cc than for rising v cc . consult the datasheet for por characteristics data.
26 xmega a4u [datasheet] 8387d?avr?02/2013 12.4.2 brownout detection the on-chip brownout detection (bod) circuit monitors the v cc level during operation by comparing it to a fixed, programmable level that is selected by the bodlevel fuses. if disabled, bod is forced on at the lowest level during chip erase and when the pdi is enabled. 12.4.3 external reset the external reset circuit is connected to the external reset pin. the external reset will trigger when the reset pin is driven below the reset pin threshold voltage, v rst , for longer than the minimum pulse period, t ext . the reset will be held as long as the pin is kept low. the reset pin includes an internal pull-up resistor. 12.4.4 watchdog reset the watchdog timer (wdt) is a system function for monitoring correct program operation. if the wdt is not reset from the software within a programmable timeout period, a watchdog reset will be given. the watchdog reset is active for one to two clock cycles of the 2mhz internal oscillator. for more details see ?wdt ? watchdog timer? on page 27 . 12.4.5 software reset the software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register.the reset will be issued within two cpu clock cycl es after writing the bit. it is not possible to execute any instruction from when a software reset is requested until it is issued. 12.4.6 program and debug interface reset the program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. this reset source is acce ssible only from external debuggers and programmers.
27 xmega a4u [datasheet] 8387d?avr?02/2013 13. wdt ? watchdog timer 13.1 features ? issues a device reset if the timer is not reset before its timeout period ? asynchronous operation from dedicated oscillator ? 1khz output of the 32khz ultra low power oscillator ? 11 selectable timeout periods, from 8ms to 8s ? two operation modes: ? normal mode ? window mode ? configuration lock to prevent unwanted changes 13.2 overview the watchdog timer (wdt) is a system function for monitoring correct program operation. it makes it possible to recover from error situations such as runaway or deadlocked code. the wdt is a timer, configured to a predefined timeout period, and is constantly running when enabled. if the wdt is not reset within the timeout period, it will issue a microcontroller reset. the wdt is reset by executing the wdr (watchdog timer reset) instruction from the application code. the window mode makes it possible to define a time slot or window inside the total timeout period during which wdt must be reset. if the wdt is reset outside this window, either too early or too late, a system reset will be issued. compared to the normal mode, this can also catch situat ions where a code error causes constant wdr execution. the wdt will run in active mode and all sleep modes, if e nabled. it is asynchronous, runs from a cpu-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail. the configuration change protection mechanism ensures that the wdt settings cannot be changed by accident. for increased safety, a fuse for locking the wdt settings is also available.
28 xmega a4u [datasheet] 8387d?avr?02/2013 14. interrupts and programmable multilevel interrupt controller 14.1 features ? short and predictable interrupt response time ? separate interrupt configuration and vector address for each interrupt ? programmable multilevel interrupt controller ? interrupt prioritizing according to level and vector address ? three selectable interrupt levels for all interrupts: low, medium and high ? selectable, round-robin priority scheme within low-level interrupts ? non-maskable interrupts for critical functions ? interrupt vectors optionally placed in the application section or the boot loader section 14.2 overview interrupts signal a change of state in peripherals, and this c an be used to alter program execution. peripherals can have one or more interrupts, and all are individually enabled and configured. when an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. the programmable multilevel interrupt controller (pmic) controls the handling and prioritizing of interrupt requests. when an interrupt request is acknowledged by the pmic, the program counter is set to point to t he interrupt vector, and the interrupt handler can be executed. all peripherals can select between three different priority leve ls for their interrupts: low, medium, and high. interrupts are prioritized according to their level and their interrupt vect or address. medium-level interrupts will interrupt low-level interrupt handlers. high-level interrupts wil l interrupt both medium- and low-level interrupt handlers. within each level, the interrupt priority is decided from the interrupt vector addres s, where the lowest interrupt vector address has the highest interrupt priority. low-level interrupts have an optional r ound-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. non-maskable interrupts (nmi) are also supported, and can be used for system critical functions. 14.3 interrupt vectors the interrupt vector is the sum of the peripheral?s base interrupt address and the offset address for specific interrupts in each peripheral. the base addresses for the atmel avr xmega a4u devices are shown in table 14-1 on page 29 . offset addresses for each interrupt available in the peri pheral are described for each peripheral in the xmega au manual. for peripherals or modules that have only one interrupt, the interrupt vector is shown in table 14-1 on page 29 . the program address is the word address.
29 xmega a4u [datasheet] 8387d?avr?02/2013 table 14-1. reset and interrupt vectors program address (base address) source interrupt description 0x000 reset 0x002 oscf_int_vect crystal oscillator failure interrupt vector (nmi) 0x004 portc_int_base port c interrupt base 0x008 portr_int_base port r interrupt base 0x00c dma_int_base dma controller interrupt base 0x014 rtc_int_base real time counter interrupt base 0x018 twic_int_base two-wire interface on port c interrupt base 0x01c tcc0_int_base timer/counter 0 on port c interrupt base 0x028 tcc1_int_base timer/counter 1 on port c interrupt base 0x030 spic_int_vect spi on port c interrupt vector 0x032 usartc0_int_base usart 0 on port c interrupt base 0x038 usartc1_int_base usart 1 on port c interrupt base 0x03e aes_int_vect aes interrupt vector 0x040 nvm_int_base nonvolatile memory interrupt base 0x044 portb_int_base port b interrupt base 0x056 porte_int_base port e interrupt base 0x05a twie_int_base two-wire interface on port e interrupt base 0x05e tce0_int_base timer/counter 0 on port e interrupt base 0x06a tce1_int_base timer/counter 1 on port e interrupt base 0x074 usarte0_int_base usart 0 on port e interrupt base 0x080 portd_int_base port d interrupt base 0x084 porta_int_base port a interrupt base 0x088 aca_int_base analog comparator on port a interrupt base 0x08e adca_int_base analog to digital converter on port a interrupt base 0x09a tcd0_int_base timer/counter 0 on port d interrupt base 0x0a6 tcd1_int_base timer/counter 1 on port d interrupt base 0x0ae spid_int_vector spi on port d interrupt vector 0x0b0 usartd0_int_base usart 0 on port d interrupt base 0x0b6 usartd1_int_base usart 1 on port d interrupt base 0x0fa usb_int_base usb on port d interrupt base
30 xmega a4u [datasheet] 8387d?avr?02/2013 15. i/o ports 15.1 features ? 34 general purpose input and output pins with individual configuration ? output driver with configurable driver and pull settings: ?totem-pole ? wired-and ?wired-or ? bus-keeper ? inverted i/o ? input with synchronous and/or asynchronous sensing with interrupts and events ? sense both edges ? sense rising edges ? sense falling edges ? sense low level ? optional pull-up and pull-down resistor on inpu t and wired-or/and configurations ? optional slew rate control ? asynchronous pin change sensing that can wake the device from all sleep modes ? two port interrupts with pin masking per i/o port ? efficient and safe access to port pins ? hardware read-modify-write through dedicated toggle/clear/set registers ? configuration of multiple pins in a single operation ? mapping of port registers into bit-accessible i/o memory space ? peripheral clocks output on port pin ? real-time counter clock output to port pin ? event channels can be output on port pin ? remapping of digital peripheral pin functions ? selectable usart, spi, and timer/counter input/output pin locations 15.2 overview one port consists of up to eight port pins: pin 0 to 7. each port pin can be configured as input or output with configurable driver and pull settings. they also implement synchronous an d asynchronous input sensing with interrupts and events for selectable pin change conditions. asynchronous pin-change sensin g means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running. all functions are individual and configurable per pin, but se veral pins can be configured in a single operation. the pins have hardware read-modify-write (rmw) functionality for safe and correct change of drive value and/or pull resistor configuration. the direction of one port pin can be changed without unintentionally changing the direction of any other pin. the port pin configuration also controls input and output selection of other device functions. it is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. the same applies to events from the event system that can be used to synchronize and cont rol external functions. other digital peripherals, such as usart, spi, and timer/counters, can be remapped to selectabl e pin locations in order to optimize pin-out versus application needs. the notation of the ports are porta, portb, portc, portd, porte, and portr. 15.3 output driver all port pins (pn) have programmable output configuration. the port pins also have configurable slew rate limitation to reduce electromagnetic emission.
31 xmega a4u [datasheet] 8387d?avr?02/2013 15.3.1 push-pull figure 15-1. i/o configuration - totem-pole. 15.3.2 pull-down figure 15-2. i/o configuration - totem-pole with pull-down (on input). 15.3.3 pull-up figure 15-3. i/o configuration - totem-pole with pull-up (on input). 15.3.4 bus-keeper the bus-keeper?s weak output produces the same logical level as the last output level. it acts as a pull-up if the last level was ?1?, and pull-down if the last level was ?0?. inn outn dirn pn inn outn dirn pn inn outn dirn pn
32 xmega a4u [datasheet] 8387d?avr?02/2013 figure 15-4. i/o configuration - totem-pole with bus-keeper. 15.3.5 others figure 15-5. output configuration - wired-or with optional pull-down. figure 15-6. i/o conf iguration - wired-and wi th optional pull-up. inn outn dirn pn inn outn pn inn outn pn
33 xmega a4u [datasheet] 8387d?avr?02/2013 15.4 input sensing input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in figure 15-7 . figure 15-7. input sensing system overview. when a pin is configured with inverted i/o, the pin value is inverted before the input sensing. 15.5 alternate port functions most port pins have alternate pin functions in addition to being a general purpose i/o pin. when an alternate function is enabled, it might override the normal port pin function or pin va lue. this happens when other per ipherals that require pins are enabled or configured to use pins. if and how a peripheral will override and use pins is described in the section for that peripheral. ?pinout and pin functions? on page 55 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin. inverted i/o interrupt control ireq event pn d q r d q r synchronizer inn edge detect asynchronous sensing synchronous sensing edge detect
34 xmega a4u [datasheet] 8387d?avr?02/2013 16. tc0/1 ? 16-bit timer/ counter type 0 and 1 16.1 features ? five 16-bit timer/counters ? three timer/coun ters of type 0 ? two timer/counters of type 1 ? split-mode enabling two 8-bit timer/co unter from each ti mer/counter type 0 ? 32-bit timer/counter support by cascading two timer/counters ? up to four compare or capture (cc) channels ? four cc channels for timer/counters of type 0 ? two cc channels for timer/counters of type 1 ? double buffered timer period setting ? double buffered capture or compare channels ? waveform generation: ? frequency generation ? single-slope pulse width modulation ? dual-slope pulse width modulation ? input capture: ? input capture with noise cancelling ? frequency capture ? pulse width capture ? 32-bit input capture ? timer overflow and error interrupts/events ? one compare match or input capture interrupt/event per cc channel ? can be used with event system for: ? quadrature decoding ? count and direction control ?capture ? can be used with dma and to trigger dma transactions ? high-resolution extension ? increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit) ? advanced waveform extension: ? low- and high-side output with programmable dead-time insertion (dti) ? event controlled fault protection for safe disabling of drivers 16.2 overview atmel avr xmega devices have a set of five flexible 16-bit timer/counters (tc). their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture. a timer/counter consists of a base counter and a set of compare or capture (cc) channels. the base counter can be used to count clock cycles or events. it has direction control and period setting that can be used for timing. the cc channels can be used together with the base counter to do compare match control, frequency generation, and pulse width waveform modulation, as well as various input capture operations. a timer/counter can be configured for either capture or compare functions, but cannot perform both at the same time. a timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. the event system can also be used for direction cont rol and capture trigger or to synchronize operations. there are two differences between timer/counter type 0 and type 1. timer/counter 0 has four cc channels, and timer/counter 1 has two cc channels. all information related to cc channels 3 and 4 is valid only for timer/counter 0. only timer/counter 0 has the split mode feature that split it into two 8-bit timer/counters with four compare channels each. some timer/counters have extensions to enable more specialized waveform and frequency generation. the advanced waveform extension (awex) is intended for motor control and other power control applications. it enables low- and high-
35 xmega a4u [datasheet] 8387d?avr?02/2013 side output with dead-time insertion, as well as fault protecti on for disabling and shutting down external drivers. it can also generate a synchronized bit pattern across the port pins. the advanced waveform extension can be enabled to provide extra and more advanced features for the timer/counter. this are only available for timer/counter 0. see ?awex ? advanced waveform extension? on page 37 for more details. the high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by using an internal clock source running up to four times faster than the peripheral clock. see ?hi-res ? high resolution extension? on page 38 for more details. figure 16-1. overview of a timer/coun ter and closely related peripherals. portc and portd each has one timer/counter 0 and one timer/counter1. porte has one timer/conter0. notation of these are tcc0 (time/counter c0), tcc1, tcd0, tcd1 and tce0, respectively. awex compare/capture channel d compare/capture channel c compare/capture channel b compare/capture channel a waveform generation buffer comparator hi-res fault protection capture control base counter counter control logic timer period prescaler dead-time insertion pattern generation clk per4 port event system clk per timer/counter
36 xmega a4u [datasheet] 8387d?avr?02/2013 17. tc2 - timer/counter type 2 17.1 features ? six eight-bit timer/counters ? three low-byte timer/counter ? three high-byte timer/counter ? up to eight compare channels in each timer/counter 2 ? four compare channels for the low-byte timer/counter ? four compare channels for the high-byte timer/counter ? waveform generation ? single slope pulse width modulation ? timer underflow interrupts/events ? one compare match interrupt/event per compar e channel for the low- byte timer/counter ? can be used with the event system for count control ? can be used to trigger dma transactions 17.2 overview there are four timer/counter 2. these are realized when a timer/counter 0 is set in split mode. it is then a system of two eight-bit timer/counters, each with four compare channels. this results in eight configurable pulse width modulation (pwm) channels with individually controlled duty cycles, and is intended for applications that require a high number of pwm channels. the two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter, respectively. the difference between them is that only the low-byte timer/counter can be used to generate compare match interrupts, events and dma triggers. the two eight-bit timer/counters have a shared clock source and separate period and compare settings. they can be clocked and timed from the peripheral clock, with opt ional prescaling, or from the event system. the counters are always counting down. portc, and portd each has one timer/counter 2. notation of these are tcc2 (time/counter c2) and tcd2, respectively.
37 xmega a4u [datasheet] 8387d?avr?02/2013 18. awex ? advanced waveform extension 18.1 features ? waveform output with complementary output from each compare channel ? four dead-time insertion (dti) units ? 8-bit resolution ? separate high and low side dead-time setting ? double buffered dead time ? optionally halts timer during dead-time insertion ? pattern generation unit creating synchronised bit pattern across the port pins ? double buffered pattern generation ? optional distribution of one compare channel output across the port pins ? event controlled fault protection for in stant and predictable fault triggering 18.2 overview the advanced waveform extension (awex) provides extra func tions to the timer/counter in waveform generation (wg) modes. it is primarily intended for use with different types of motor control and other power control applications. it enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external drivers. it can also generate a synchronized bit pattern across the port pins. each of the waveform generator outputs from the timer/count er 0 are split into a complimentary pair of outputs when any awex features are enabled. these output pairs go through a dead-time insertion (dti) unit that generates the non- inverted low side (ls) and inverted high side (hs) of the wg output with dead-time insertion between ls and hs switching. the dti output will override the normal port value according to the port override setting. the pattern generation unit can be used to generate a synchroniz ed bit pattern on the port it is connected to. in addition, the wg output from compare channel a can be distributed to and override all the port pins. when the pattern generator unit is enabled, the dti unit is bypassed. the fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable the awex output. the event system ensures predictable and instant fault reaction, and gives flexibility in the selection of fault triggers. the awex is available for tcc0. the notation of this is awexc.
38 xmega a4u [datasheet] 8387d?avr?02/2013 19. hi-res ? high r esolution extension 19.1 features ? increases waveform generator resolution up to 8x (three bits) ? supports frequency, single-slope pwm, and dual-slope pwm generation ? supports the awex when this is used for the sam e timer/counter 19.2 overview the high-resolution (hi-res) extension can be used to in crease the resolution of the waveform generation output from a timer/counter by four or eight. it can be used for a timer/counter doing frequency, single-slope pwm, or dual-slope pwm generation. it can also be used with th e awex if this is used for the same timer/counter. the hi-res extension uses the peripheral 4x clock (clk per4 ). the system clock prescalers must be configured so the peripheral 4x clock frequency is four times higher than t he peripheral and cpu clock frequency when the hi-res extension is enabled. there are three hi-res extensions that each can be enabled for each timer/counters pair on portc, portd and porte. the notation of these are hiresc, hiresd and hirese, respectively.
39 xmega a4u [datasheet] 8387d?avr?02/2013 20. rtc ? 16-bit real-time counter 20.1 features ? 16-bit resolution ? selectable clock source ? 32.768khz external crystal ? external clock ? 32.768khz internal oscillator ? 32khz internal ulp oscillator ? programmable 10-bit clock prescaling ? one compare register ? one period register ? clear counter on period overflow ? optional interrupt/event on overflow and compare match 20.2 overview the 16-bit real-time counter (rtc) is a counter that typica lly runs continuously, including in low-power sleep modes, to keep track of time. it can wake up the device from sleep modes and/or interrupt the device at regular intervals. the reference clock is typically the 1.024khz output from a high-accuracy crystal of 32.768khz, and this is the configuration most optimized for low power consumption. the faster 32.768khz output can be selected if the rtc needs a resolution higher than 1ms. the rtc can also be clock ed from an external clock signal, the 32.768khz internal oscillator or the 32khz internal ulp oscillator. the rtc includes a 10-bit programmable prescaler that c an scale down the reference clock before it reaches the counter. a wide range of resolutions and time-out periods can be configured. with a 32.768khz clock source, the maximum resolution is 30.5s, and time-out periods can range up to 2000 seconds. with a resolution of 1s, the maximum timeout period is more than18 hours (65536 seconds). the rtc can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period register value. figure 20-1. real-time counter overview. 32.768khz crystal osc 32.768khz int. osc tosc1 tosc2 external clock div32 div32 32khz int ulp (div32) rtcsrc 10-bit prescaler clk rtc cnt per comp = = ?match?/ compare top/ overflow
40 xmega a4u [datasheet] 8387d?avr?02/2013 21. usb ? universal se rial bus interface 21.1 features ? one usb 2.0 full speed (12mbps) and low speed (1.5mbps) device compliant interface ? integrated on-chip usb transceiver, no external components needed ? 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints ? one input endpoint per endpoint address ? one output endpoint per endpoint address ? endpoint address transfer type selectable to ? control transfers ? interrupt transfers ? bulk transfers ? isochronous transfers ? configurable data payload size per endpoint, up to 1023 bytes ? endpoint configuration and data buffers located in internal sram ? configurable location for endpoint configuration data ? configurable location for each endpoint's data buffer ? built-in direct memory access (dma) to internal sram for: ? endpoint configurations ? reading and writing endpoint data ? ping-pong operation for higher throughput and double buffered operation ? input and output endpoint data buffers used in a single direction ? cpu/dma controller can update data buffer during transfer ? multipacket transfer for reduced interrupt load and software intervention ? data payload exceeding maximum packet size is transferred in one continuous transfer ? no interrupts or software interaction on packet transaction level ? transaction complete fifo for workflow ma nagement when using multiple endpoints ? tracks all completed transactions in a first-come, first-served work queue ? clock selection independent of system clock source and selection ? minimum 1.5mhz cpu clock required for low speed usb operation ? minimum 12mhz cpu clock required for full speed operation ? connection to event system ? on chip debug possibilities during usb transactions 21.2 overview the usb module is a usb 2.0 full speed (12mbps) and low speed (1.5mbps) device compliant interface. the usb supports 16 endpoint addresses. all endpoint addresses have one input and one output endpoint, for a total of 31 configurable endpoints and one control endpoint. each endpoint address is fully configurable and can be configured for any of the four transfer types; control, interrupt, bulk, or isochronous. the data payload size is also selectable, and it supports data payloads up to 1023 bytes. no dedicated memory is allocated for or included in the usb module. internal sram is used to keep the configuration for each endpoint address and the data buffer for each endpoint. the memory locations used for endpoint configurations and data buffers are fully configurable. the amount of memory allocated is fully dynamic, according to the number of endpoints in use and the configuration of these. the usb module has built-in direct memory access (dma), and will read/write data from/to the sram when a usb transaction takes place. to maximize throughput, an endpoint address can be configured for ping-pong operation. when done, the input and output endpoints are both used in the same direction. the cpu or dma controller can then read/write one data buffer while the usb module writes/reads the others, and vice versa. this gives double buffered communication.
41 xmega a4u [datasheet] 8387d?avr?02/2013 multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. this reduces the cpu intervention and the interrupts needed for usb transfers. for low-power operation, the usb module can put the microc ontroller into any sleep mode when the usb bus is idle and a suspend condition is given. upon bus resumes, the usb module can wake up the microcontroller from any sleep mode. portd has one usb. notation of this is usb.
42 xmega a4u [datasheet] 8387d?avr?02/2013 22. twi ? two-wire interface 22.1 features ? two identical two-wire interface peripherals ? bidirectional, two-wir e communication interface ? phillips i 2 c compatible ? system management bus (smbus) compatible ? bus master and slave operation supported ? slave operation ? single bus master operation ? bus master in multi-master bus environment ? multi-master arbitration ? flexible slave address match functions ? 7-bit and general call address recognition in hardware ? 10-bit addressing supported ? address mask register for dual address match or address range masking ? optional software address recognition for unlimited number of addresses ? slave can operate in all sleep modes, including power-down ? slave address match can wake device from all sleep modes ? 100khz and 400khz bus frequency support ? slew-rate limited output drivers ? input filter for bus noise and spike suppression ? support arbitration between start/repeated start and data bit (smbus) ? slave arbitration allows support for address resolve protocol (arp) (smbus) 22.2 overview the two-wire interface (twi) is a bidirectional, two-wire communication interface. it is i 2 c and system management bus (smbus) compatible. the only external hardware needed to im plement the bus is one pull-up resistor on each bus line. a device connected to the bus must act as a master or a slave. the master initiates a data transaction by addressing a slave on the bus and telling whether it wants to transmit or receive data. one bus can have many slaves and one or several masters that can take control of the bus. an arbitration process handles priority if more than one master tries to transmit data at the same time. mechanisms for resolving bus contention are inherent in the protocol. the twi module supports master and slave functionality. t he master and slave functionality are separated from each other, and can be enabled and configured separately. the ma ster module supports multi-master bus operation and arbitration. it contains the baud rate generator. both 100khz and 400khz bus frequency is supported. quick command and smart mode can be enabled to auto-trigger operations and reduce software complexity. the slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. a dedicated address mask register can act as a second address match register or as a register for address range masking. the slave continues to operate in all sleep modes, including power-down mode. this enables the slave to wake up the device from all sleep modes on twi address match. it is possible to disable the address matching to let this be handled in software instead. the twi module will detect start and stop conditions, bus collisions, and bus errors. arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes. it is possible to disable the twi drivers in the device, and enable a four-wire digital interface for connecting to an external twi bus driver. this can be used for applications where the device operates from a different v cc voltage than used by the twi bus. portc and porte each has one twi. notation of these peripherals are twic and twie.
43 xmega a4u [datasheet] 8387d?avr?02/2013 23. spi ? serial pe ripheral interface 23.1 features ? two identical spi peripherals ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? eight programmable bit rates ? interrupt flag at the end of transmission ? write collision flag to indicate data collision ? wake up from idle sleep mode ? double speed master mode 23.2 overview the serial peripheral interface (spi) is a high-speed synchr onous data transfer interface using three or four pins. it allows fast communication between an atmel avr xmega device and peripheral devices or between several microcontrollers. the spi supports full-duplex communication. a device connected to the bus must act as a master or slave. the master initiates and controls all data transactions. portc and portd each has one spi. notation of these peripherals are spic and spid.
44 xmega a4u [datasheet] 8387d?avr?02/2013 24. usart 24.1 features ? five identical usart peripherals ? full-duplex operation ? asynchronous or synchronous operation ? synchronous clock rates up to 1/2 of the device clock frequency ? asynchronous clock rates up to 1/8 of the device clock frequency ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? fractional baud rate generator ? can generate desired baud rate from any system clock frequency ? no need for external oscillator with certain frequencies ? built-in error detection and correction schemes ? odd or even parity generation and parity check ? data overrun and framing error detection ? noise filtering includes false start bi t detection and digital low-pass filter ? separate interrupts for ? transmit complete ? transmit data register empty ? receive complete ? multiprocessor communication mode ? addressing scheme to address a specific devices on a multidevice bus ? enable unaddressed devices to automatically ignore all frames ? master spi mode ? double buffered operation ? operation up to 1/2 of the peripheral clock frequency ? ircom module for irda compliant pulse modulation/demodulation 24.2 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) is a fast and flexible serial communication module. the usart supports full-duplex communication and asynchronous and synchronous operation. the usart can be configured to operate in spi master mode and used for spi communication. communication is frame based, and the frame format c an be customized to support a wide range of standards. the usart is buffered in both directions, enabling continued dat a transmission without any delay between frames. separate interrupts for receive and transmit complete enable fully interrupt driven communication. frame error and buffer overflow are detected in hardware and indicated with separate st atus flags. even or odd parity generation and parity check can also be enabled. the clock generator includes a fractional baud rate generator that is able to generate a wide range of usart baud rates from any system clock frequencies. this removes the need to use an external crystal oscillator with a specific frequency to achieve a required baud rate. it also supports ex ternal clock input in synchronous slave operation. when the usart is set in master spi mode, all usart-spec ific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. pin control and interrupt generation are identical in both modes. the registers are used in both modes, but their functionality differs for some control settings. an ircom module can be enabled for one usart to suppor t irda 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2kbps. portc and portd each has two usarts. porte has one us art. notation of these peripherals are usartc0, usartc1, usartd0, usartd1 and usarte0, respectively.
45 xmega a4u [datasheet] 8387d?avr?02/2013 25. ircom ? ir communication module 25.1 features ? pulse modulation/demodulation for infrared communication ? irda compatible for baud rates up to 115.2kbps ? selectable pulse modulation scheme ? 3/16 of the baud rate period ? fixed pulse period, 8-bit programmable ? pulse modulation disabled ? built-in filtering ? can be connected to and used by any usart 25.2 overview atmel avr xmega devices contain an infrared communication mo dule (ircom) that is irda compatible for baud rates up to 115.2kbps. it can be connected to any usart to enable infrared pulse encoding/decoding for that usart.
46 xmega a4u [datasheet] 8387d?avr?02/2013 26. aes and des crypto engine 26.1 features ? data encryption standard (des) cpu instruction ? advanced encryption standard (aes) crypto module ? des instruction ? encryption and decryption ? des supported ? encryption/decryption in 16 cpu clock cycles per 8-byte block ? aes crypto module ? encryption and decryption ? supports 128-bit keys ? supports xor data load mode to the state memory ? encryption/decryption in 375 clock cycles per 16-byte block 26.2 overview the advanced encryption standard (aes) and data encryp tion standard (des) are two commonly used standards for cryptography. these are supported th rough an aes peripheral module and a des cpu instruction, and the communication interfaces and the cpu can use these for fast, encrypted communication and secure data storage. des is supported by an instruction in the avr cpu. the 8-byte key and 8-byte data blocks must be loaded into the register file, and then the des instruction must be executed 16 times to encrypt/decrypt the data block. the aes crypto module encrypts and decrypts 128-bit data blo cks with the use of a 128-bit key. the key and data must be loaded into the key and state memory in the module before encryption/decryption is started. it takes 375 peripheral clock cycles before the encryption/decryption is done. the encrypted/encrypted data can then be read out, and an optional interrupt can be generated. the aes crypto m odule also has dma support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
47 xmega a4u [datasheet] 8387d?avr?02/2013 27. crc ? cyclic redu ndancy check generator 27.1 features ? cyclic redundancy check (crc) generation and checking for ? communication data ? program or data in flash memory ? data in sram and i/o memory space ? integrated with fl ash memory, dma controller and cpu ? continuous crc on data go ing through a dma channel ? automatic crc of the complete or a selectable range of the flash memory ? cpu can load data to the crc ge nerator through th e i/o interface ? crc polynomial software selectable to ? crc-16 (crc-ccitt) ? crc-32 (ieee 802.3) ? zero remainder detection 27.2 overview a cyclic redundancy check (crc) is an error detection technique test algorithm used to find accidental errors in data, and it is commonly used to determine the correctness of a dat a transmission, and data present in the data and program memories. a crc takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. when the same data are later received or read, the device or application repeats the calculation. if the new crc result does not match the one calculated earlier, the block contains a data error. the application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. typically, an n-bit crc applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2 -n of all longer error bursts. the crc module in atmel avr xmega devices s upports two commonly used crc polynomials; crc-16 (crc- ccitt) and crc-32 (ieee 802.3). ? crc-16: ? crc-32: polynomial: x 16 +x 12 +x 5 +1 hex value: 0x1021 polynomial: x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1 hex value: 0x04c11db7
48 xmega a4u [datasheet] 8387d?avr?02/2013 28. adc ? 12-bit analog to digital converter 28.1 features ? one analog to digi tal converter (adc) ? 12-bit resolution ? up to two million samples per second ? two inputs can be sampled simult aneously using adc and 1x gain stage ? four inputs can be sampled within 1.5s ? down to 2.5s conversion time with 8-bit resolution ? down to 3.5s conversion time with 12-bit resolution ? differential and single-ended input ? up to 12 single-ended inputs ? 12x4 differential inputs without gain ? 8x4 differential inputs with gain ? built-in differential gain stage ? 1/2 x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options ? single, continuous and scan conversion options ? four internal inputs ? internal temperature sensor ? dac output ?v cc voltage divided by 10 ? 1.1v bandgap voltage ? four conversion channels with individu al input control and result registers ? enable four parallel configurations and results ? internal and external reference options ? compare function for accurate monitoring of user defined thresholds ? optional event triggered conversion for accurate timing ? optional dma transfer of conversion results ? optional interrupt/event on compare result 28.2 overview the adc converts analog signals to digital values. the adc has 12-bit resolution and is capable of converting up to two million samples per second (msps). the input selection is flexible, and both single-ended and differential measurements can be done. for differential measurements, an optional gai n stage is available to increase the dynamic range. in addition, several internal signal inputs are avail able. the adc can provide both signed and unsigned results. this is a pipelined adc that consists of several consecutiv e stages. the pipelined design allows a high sample rate at a low system clock frequency. it also means that a new input can be sampled and a new adc conversion started while other adc conversions are still ongoing. this removes dependencies between sample rate and propagation delay. the adc has four conversion channels (0-3) with individual input selection, result registers, and conversion start control. the adc can then keep and use four parallel configurations and results, and this will ease use for applications with high data throughput or for multiple modules using the adc independe ntly. it is possible to use dma to move adc results directly to memory or peripherals when conversions are done. both internal and external reference voltages can be used. an integrated temperature sensor is available for use with the adc. the output from the dac, v cc /10 and the bandgap voltage can also be measured by the adc. the adc has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required.
49 xmega a4u [datasheet] 8387d?avr?02/2013 figure 28-1. adc overview. two inputs can be sampled simultaneously as both the adc and the gain stage include sample and hold circuits, and the gain stage has 1x gain setting. four inputs can be sampled within 1.5s without any intervention by the application. the adc may be configured for 8- or 12-bit result, reducing the minimum conversion time (p ropagation delay) from 3.5s for 12-bit to 2.5s for 8-bit result. adc conversion results are provided left- or right adjusted with optional ?1? or ?0? padding. this eases calculation when the result is represented as a signed integer (signed 16-bit number). porta has one adc. notation of this peripheral is adca. ch1 result ch0 result ch2 result compare < > threshold (int req) internal 1.00v internal vcc/1.6v arefa arefb v inp v inn internal signals internal vcc/2 internal signals ch3 result adc0 adc7 adc4 adc7 adc0 adc3 ? ? ? int. signals int. signals reference voltage ?x - 64x ? ? ? ? ? ? adc0 adc11 ? ? ?
50 xmega a4u [datasheet] 8387d?avr?02/2013 29. dac ? 12-bit digital to analog converter 29.1 features ? one digital to anal og converter (dac) ? 12-bit resolution ? two independent, continuous-drive output channels ? up to one million sampl es per second conversion rate per dac channel ? built-in calibration that removes: ? offset error ? gain error ? multiple conversion trigger sources ? on new available data ? events from the event system ? high drive capabilities and support for ? resistive loads ? capacitive loads ? combined resistive and capacitive loads ? internal and external reference options ? dac output available as input to analog comparator and adc ? low-power mode, with reduced drive strength ? optional dma transfer of data 29.2 overview the digital-to-analog converter (dac) converts digital val ues to voltages. the dac has two channels, each with 12-bit resolution, and is capable of converting up to one million samples per second (msps) on each channel. the built-in calibration system can remove offset and gain error when loaded with calibration values from software. figure 29-1. dac overview. a dac conversion is automatically started when new data to be converted are available. events from the event system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the dac and other peripherals, such as a timer/counter. the dma controller can be used to transfer data to the dac. the dac has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads which combine both. a low-power mode is available, which will r educe the drive strength of the output. internal and external dac0 dac1 ctrla ch1data ch0data trigger trigger internal output enable enable internal 1.00v arefa arefb reference selection avcc output driver output driver d a t a int. driver d a t a ctrlb dma req (data empty) dma req (data empty) select 12 12 select enable to ac/adc
51 xmega a4u [datasheet] 8387d?avr?02/2013 voltage references can be used. the dac output is also interna lly available for use as input to the analog comparator or adc. portb has one dac. notation of this peripheral is dacb.
52 xmega a4u [datasheet] 8387d?avr?02/2013 30. ac ? analog comparator 30.1 features ? two analog comparators (acs) ? selectable propagation delay versus current consumption ? selectable hysteresis ?no ?small ?large ? analog comparator output available on pin ? flexible input selection ? all pins on the port ? output from the dac ? bandgap reference voltage ? a 64-level programmable voltage scaler of the internal v cc voltage ? interrupt and even t generation on: ? rising edge ? falling edge ? toggle ? window function interrupt and event generation on: ? signal above window ? signal inside window ? signal below window ? constant current source with configurable output pin selection 30.2 overview the analog comparator (ac) compares the voltage levels on two inputs and gives a digital output based on this comparison. the analog comparator may be configured to generate interrupt requests and/or events upon several different combinations of input change. two important properties of the analog comparator?s dynamic behavior are: hysteresis and propagation delay. both of these parameters may be adjusted in order to achieve the optimal operation for each application. the input selection includes analog port pins, several inter nal signals, and a 64-level programmable voltage scaler. the analog comparator output state can also be output on a pin for use by external devices. a constant current source can be enabled and output on a selectable pin. this can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications. the analog comparators are always grouped in pairs on eac h port. these are called analog comparator 0 (ac0) and analog comparator 1 (ac1). they have identical behavior, but separate control registers. used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level. porta has one ac pair. notation is aca.
53 xmega a4u [datasheet] 8387d?avr?02/2013 figure 30-1. analog comparator overview. the window function is realized by connecting the external i nputs of the two analog comparators in a pair as shown in figure 30-2 . figure 30-2. analog comparator window function. voltage scaler acnmuxctrl acnctrl interrupt mode enable enable hysteresis hysteresis dac bandgap ac1out winctrl interrupt sensititivity control & window function events interrupts ac0out pin input pin input pin input pin input ac0 + - ac1 + - input signal upper limit of window lower limit of window interrupt sensitivity control interrupts events
54 xmega a4u [datasheet] 8387d?avr?02/2013 31. programming and debugging 31.1 features ? programming ? external programming through pdi interface minimal protocol overhead for fast operation built-in error detection and handling for reliable operation ? boot loader support for programming through any communication interface ? debugging ? nonintrusive, real-time, on-chip debug system ? no software or hardware resources required from device except pin connection ? program flow control go, stop, reset, step into, step over, step out, run-to-cursor ? unlimited number of user program breakpoints ? unlimited number of user data breakpoints, break on: data location read, write, or both read and write data location content equal or not equal to a value data location content is greater or smaller than a value data location content is within or outside a range ? no limitation on device clock frequency ? program and debug interface (pdi) ? two-pin interface for external programming and debugging ? uses the reset pin and a dedicated pin ? no i/o pins required during programming or debugging 31.2 overview the program and debug interface (pdi) is an atmel proprie tary interface for external programming and on-chip debugging of a device. the pdi supports fast programming of nonvolatile memory (n vm) spaces; flash, eepom, fuses, lock bits, and the user signature row. debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. it does not require any software or hardware resources except for the device pin connection. using the atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. application debug can be done from a c or other high-level language source code level, as well as from an assembler and disassembler level. programming and debugging can be done through two physical interf aces. the primary one is the pdi physical layer, which is available on all devices. this is a two-pin interface that uses the reset pin for the clock input (pdi_clk) and one other dedicated pin for data input and output (pdi_data). a jt ag interface is also available on most devices, and this can be used for programming and debugging through the four-pin jt ag interface. the jtag interface is ieee std. 1149.1 compliant, and supports boundary scan. any external pr ogrammer or on-chip debugger/emulator can be directly connected to either of these interfaces. unless otherwise stated, all references to the pdi assume access through the pdi physical layer.
55 xmega a4u [datasheet] 8387d?avr?02/2013 32. pinout and pin functions the device pinout is shown in ?pinout/block diagram? on page 3 . in addition to general purpose i/o functionality, each pin can have several alternate functions. this will depend on which peripheral is enabled and connected to the actual pin. only one of the pin functions can be used at time. 32.1 alternate pin f unction description the tables below show the notation for all pin functions available and describe its function. 32.1.1 operation/power supply 32.1.2 port interrupt functions 32.1.3 analog functions 32.1.4 timer/counter and awex functions v cc digital supply voltage av cc analog supply voltage gnd ground sync port pin with full synchronous and limi ted asynchronous interrupt function async port pin with full synchronous and full asynchronous interrupt function acn analog comparator input pin n acnout analog comparator n output adcn analog to digital converter input pin n dacn digital to analog converter output pin n a ref analog reference input pin ocnxls output compare channel x low side for timer/counter n ocnxhs output compare channel x high side for timer/counter n
56 xmega a4u [datasheet] 8387d?avr?02/2013 32.1.5 communication functions 32.1.6 oscillators, clock and event 32.1.7 debug/system functions scl serial clock for twi sda serial data for twi sclin serial clock in for twi when external driver interface is enabled sclout serial clock out for twi when external driver interface is enabled sdain serial data in for twi when external driver interface is enabled sdaout serial data out for twi when external driver interface is enabled xckn transfer clock for usart n rxdn receiver data for usart n txdn transmitter data for usart n ss slave select for spi mosi master out slave in for spi miso master in slave out for spi sck serial clock for spi d- data- for usb d+ data+ for usb toscn timer oscillator pin n xtaln input/output for oscillator pin n clkout peripheral clock output evout event channel output rtcout rtc clock source output reset reset pin pdi_clk program and debug interface clock pin pdi_data program and debug interface data pin
57 xmega a4u [datasheet] 8387d?avr?02/2013 32.2 alternate pin functions the tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. the head row shows what peripheral that enable and use the alternate pin functions. for better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under th e first table where this apply. table 32-1. port a - alternate functions. table 32-2. port b - alternate functions. port a pin # interrupt adca pos/gainpos adca neg adca gainneg aca pos aca neg aca out refa gnd 38 avcc 39 pa0 40 sync adc0 adc0 ac0 ac0 aref pa1 41 sync adc1 adc1 ac1 ac1 pa2 42 sync/async adc2 adc2 ac2 pa3 43 sync adc3 adc3 ac3 ac3 pa4 44 sync adc4 adc4 ac4 pa5 1 sync adc5 adc5 ac5 ac5 pa6 2 sync adc6 adc6 ac6 ac1out pa7 3 sync adc7 adc7 ac7 ac0out port b pin # interrupt adca pos dacb refb pb0 4 sync adc8 aref pb1 5 sync adc9 pb2 6 sync/async adc10 dac0 pb3 7 sync adc11 dac1
58 xmega a4u [datasheet] 8387d?avr?02/2013 table 32-3. port c - alternate functions. notes: 1. pin mapping of all tc0 can optionally be moved to high nibble of port 2. if tc0 is configured as tc2 all eight pins can be used for pwm output. 3. pin mapping of all usart0 can optionally be moved to high nibble of port. 4. pins mosi and sck for all spi can optionally be swapped. 5. clkout can optionally be moved between port c, d and e and between pin 4 and 7. 6. evout can optionally be moved between port c, d and e and between pin 4 and 7. table 32-4. port d - alternate functions. port c pin # interrupt tcc0 (1)(2) awexc tcc1 usart c0 (3) usart c1 spic (4) twic twic w/ext driver clockout (5) eventout (6) gnd 8 vcc 9 pc0 10 sync oc0a oc0als sda sdain pc1 11 sync oc0b oc0ahs xck0 scl sclin pc2 12 sync/ async oc0c oc0bls rxd0 sdaout pc3 13 sync oc0d oc0bhs txd0 sclout pc4 14 sync oc0cls oc1a ss pc5 15 sync oc0chs oc1b xck1 mosi pc6 16 sync oc0dls rxd1 miso clk rtc pc7 17 sync oc0dhs txd1 sck clk per evout port d pin # interrupt tcd0 tcd1 usb usartd0 usartd1 spid clockout eventout gnd 18 vcc 19 pd0 20 sync oc0a pd1 21 sync oc0b xck0 pd2 22 sync/async oc0c rxd0 pd3 23 sync oc0d txd0 pd4 24 sync oc1a ss pd5 25 sync oc1b xck1 mosi pd6 26 sync d- rxd1 miso pd7 27 sync d+ txd1 sck clk per evout
59 xmega a4u [datasheet] 8387d?avr?02/2013 table 32-5. port e - alternate functions. table 32-6. port r - alternate functions. note: 1. tosc pins can optionally be moved to pe2/pe3. port e pin # interrupt tce0 usarte0 twie pe0 28 sync oc0a sda pe1 29 sync oc0b xck0 scl gnd 30 vcc 31 pe2 32 sync/async oc0c rxd0 pe3 33 sync oc0d txd0 port r pin # interrupt pdi xtal tosc (1) pdi 34 pdi_data reset 35 pdi_clock pr0 36 sync xtal2 tosc2 pr1 37 sync xtal1 tosc1
60 xmega a4u [datasheet] 8387d?avr?02/2013 33. peripheral modu le address map the address maps show the base address for each peripheral and module in atmel avr xmega a4u. for complete register description and summary for each peripheral module, refer to the xmega au manual. table 33-1. peripheral module address map. base address name description 0x0000 gpio general purpose io registers 0x0010 vport0 virtual port 0 0x0014 vport1 virtual port 1 0x0018 vport2 virtual port 2 0x001c vport3 virtual port 2 0x0030 cpu cpu 0x0040 clk clock control 0x0048 sleep sleep controller 0x0050 osc oscillator control 0x0060 dfllrc32m dfll for the 32mhz internal rc oscillator 0x0068 dfllrc2m dfll for the 2mhz rc oscillator 0x0070 pr power reduction 0x0078 rst reset controller 0x0080 wdt watch-dog timer 0x0090 mcu mcu control 0x00a0 pmic programmable multilevel interrupt controller 0x00b0 portcfg port configuration 0x00c0 aes aes module 0x00d0 crc crc module 0x0100 dma dma module 0x0180 evsys event system 0x01c0 nvm non volatile memory (nvm) controller 0x0200 adca analog to digital converter on port a 0x0380 aca analog comparator pair on port a 0x0400 rtc real time counter 0x0480 twic two wire interface on port c 0x04a0 twie two wire interface on port e 0x04c0 usb universal serial bus interface 0x0600 porta port a
61 xmega a4u [datasheet] 8387d?avr?02/2013 0x0620 portb port b 0x0640 portc port c 0x0660 portd port d 0x0680 porte port e 0x07e0 portr port r 0x0800 tcc0 timer/counter 0 on port c 0x0840 tcc1 timer/counter 1 on port c 0x0880 awexc advanced waveform extension on port c 0x0890 hiresc high resolution extension on port c 0x08a0 usartc0 usart 0 on port c 0x08b0 usartc1 usart 1 on port c 0x08c0 spic serial peripheral interface on port c 0x08f8 ircom infrared communication module 0x0900 tcd0 timer/counter 0 on port d 0x0940 tcd1 timer/counter 1 on port d 0x0990 hiresd high resolution extension on port d 0x09a0 usartd0 usart 0 on port d 0x09b0 usartd1 usart 1 on port d 0x09c0 spid serial peripheral interface on port d 0x0a00 tce0 timer/counter 0 on port e 0x0a80 awexe advanced waveform extensionon port e 0x0a90 hirese high resolution extension on port e 0x0aa0 usarte0 usart 0 on port e base address name description
62 xmega a4u [datasheet] 8387d?avr?02/2013 34. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add without carry rd ? rd + rr z,c,n,v,s,h 1 adc rd, rr add with carry rd ? rd + rr + c z,c,n,v,s,h 1 adiw rd, k add immediate to word rd ? rd + 1:rd + k z,c,n,v,s 2 sub rd, rr subtract without carry rd ? rd - rr z,c,n,v,s,h 1 subi rd, k subtract immediate rd ? rd - k z,c,n,v,s,h 1 sbc rd, rr subtract with carry rd ? rd - rr - c z,c,n,v,s,h 1 sbci rd, k subtract immediate with carry rd ? rd - k - c z,c,n,v,s,h 1 sbiw rd, k subtract immediate from word rd + 1:rd ? rd + 1:rd - k z,c,n,v,s 2 and rd, rr logical and rd ? rd ? rr z,n,v,s 1 andi rd, k logical and with immediate rd ? rd ? k z,n,v,s 1 or rd, rr logical or rd ? rd v rr z,n,v,s 1 ori rd, k logical or with immediate rd ? rd v k z,n,v,s 1 eor rd, rr exclusive or rd ? rd ? rr z,n,v,s 1 com rd one?s complement rd ? $ff - rd z,c,n,v,s 1 neg rd two?s complement rd ? $00 - rd z,c,n,v,s,h 1 sbr rd,k set bit(s) in register rd ? rd v k z,n,v,s 1 cbr rd,k clear bit(s) in register rd ? rd ? ($ffh - k) z,n,v,s 1 inc rd increment rd ? rd + 1 z,n,v,s 1 dec rd decrement rd ? rd - 1 z,n,v,s 1 tst rd test for zero or minus rd ? rd ? rd z,n,v,s 1 clr rd clear register rd ? rd ? rd z,n,v,s 1 ser rd set register rd ? $ff none 1 mul rd,rr multiply unsigned r1:r0 ? rd x rr (uu) z,c 2 muls rd,rr multiply signed r1:r0 ? rd x rr (ss) z,c 2 mulsu rd,rr multiply signed with unsigned r1:r0 ? rd x rr (su) z,c 2 fmul rd,rr fractional multiply unsigned r1:r0 ? rd x rr<<1 (uu) z,c 2 fmuls rd,rr fractional multiply signed r1:r0 ? rd x rr<<1 (ss) z,c 2 fmulsu rd,rr fractional multiply signed with unsigned r1:r0 ? rd x rr<<1 (su) z,c 2 des k data encryption if (h = 0) then r15:r0 else if (h = 1) then r15:r0 ? ? encrypt(r15:r0, k) decrypt(r15:r0, k) 1/2 branch instructions rjmp k relative jump pc ? pc + k + 1 none 2 ijmp indirect jump to (z) pc(15:0) pc(21:16) ? ? z, 0 none 2 eijmp extended indirect jump to (z) pc(15:0) pc(21:16) ? ? z, eind none 2 jmp k jump pc ? k none 3 rcall k relative call subroutine pc ? pc + k + 1 none 2 / 3 (1)
63 xmega a4u [datasheet] 8387d?avr?02/2013 icall indirect call to (z) pc(15:0) pc(21:16) ? ? z, 0 none 2 / 3 (1) eicall extended indirect call to (z) pc(15:0) pc(21:16) ? ? z, eind none 3 (1) call k call subroutine pc ? k none 3 / 4 (1) ret subroutine return pc ? stack none 4 / 5 (1) reti interrupt return pc ? stack i 4 / 5 (1) cpse rd,rr compare, skip if equal if (rd = rr) pc ? pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd - rr z,c,n,v,s,h 1 cpc rd,rr compare with carry rd - rr - c z,c,n,v,s,h 1 cpi rd,k compare with immediate rd - k z,c,n,v,s,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc ? pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register set if (rr(b) = 1) pc ? pc + 2 or 3 none 1 / 2 / 3 sbic a, b skip if bit in i/o register cleared if (i/o(a,b) = 0) pc ? pc + 2 or 3 none 2 / 3 / 4 sbis a, b skip if bit in i/o register set if (i/o(a,b) =1) pc ? pc + 2 or 3 none 2 / 3 / 4 brbs s, k branch if status flag set if (sreg(s) = 1) then pc ? pc + k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc ? pc + k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc ? pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc ? pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc ? pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc ? pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc ? pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc ? pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc ? pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc ? pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n ? v= 0) then pc ? pc + k + 1 none 1 / 2 brlt k branch if less than, signed if (n ? v= 1) then pc ? pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc ? pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc ? pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc ? pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc ? pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc ? pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc ? pc + k + 1 none 1 / 2 brie k branch if interrupt enabled if (i = 1) then pc ? pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if (i = 0) then pc ? pc + k + 1 none 1 / 2 data transfer instructions mov rd, rr copy register rd ? rr none 1 movw rd, rr copy register pair rd+1:rd ? rr+1:rr none 1 ldi rd, k load immediate rd ? k none 1 mnemonics operands description operation flags #clocks
64 xmega a4u [datasheet] 8387d?avr?02/2013 lds rd, k load direct from data space rd ? (k) none 2 (1)(2) ld rd, x load indirect rd ? (x) none 1 (1)(2) ld rd, x+ load indirect and post-increment rd x ? ? (x) x + 1 none 1 (1)(2) ld rd, -x load indirect and pre-decrement x ? x - 1, rd ? (x) ? ? x - 1 (x) none 2 (1)(2) ld rd, y load indirect rd ? (y) ? (y) none 1 (1)(2) ld rd, y+ load indirect and post-increment rd y ? ? (y) y + 1 none 1 (1)(2) ld rd, -y load indirect and pre-decrement y rd ? ? y - 1 (y) none 2 (1)(2) ldd rd, y+q load indirect with displacement rd ? (y + q) none 2 (1)(2) ld rd, z load indirect rd ? (z) none 1 (1)(2) ld rd, z+ load indirect and post-increment rd z ? ? (z), z+1 none 1 (1)(2) ld rd, -z load indirect and pre-decrement z rd ? ? z - 1, (z) none 2 (1)(2) ldd rd, z+q load indirect with displacement rd ? (z + q) none 2 (1)(2) sts k, rr store direct to data space (k) ? rd none 2 (1) st x, rr store indirect (x) ? rr none 1 (1) st x+, rr store indirect and post-increment (x) x ? ? rr, x + 1 none 1 (1) st -x, rr store indirect and pre-decrement x (x) ? ? x - 1, rr none 2 (1) st y, r r store indirect (y) ? rr none 1 (1) st y+, rr store indirect and post-increment (y) y ? ? rr, y + 1 none 1 (1) st -y, rr store indirect and pre-decrement y (y) ? ? y - 1, rr none 2 (1) std y+q, rr store indirect with displacement (y + q) ? rr none 2 (1) st z, rr store indirect (z) ? rr none 1 (1) st z+, rr store indirect and post-increment (z) z ? ? rr z + 1 none 1 (1) st -z, rr store indirect and pre-decrement z ? z - 1 none 2 (1) std z+q,rr store indirect with displacement (z + q) ? rr none 2 (1) lpm load program memory r0 ? (z) none 3 lpm rd, z load program memory rd ? (z) none 3 lpm rd, z+ load program memory and post-increment rd z ? ? (z), z + 1 none 3 elpm extended load program memory r0 ? (rampz:z) none 3 elpm rd, z extended load program memory rd ? (rampz:z) none 3 elpm rd, z+ extended load program memory and post- increment rd z ? ? (rampz:z), z + 1 none 3 spm store program memory (rampz:z) ? r1:r0 none - spm z+ store program memory and post-increment by 2 (rampz:z) z ? ? r1:r0, z + 2 none - mnemonics operands description operation flags #clocks
65 xmega a4u [datasheet] 8387d?avr?02/2013 in rd, a in from i/o location rd ? i/o(a) none 1 out a, rr out to i/o location i/o(a) ? rr none 1 push rr push register on stack stack ? rr none 1 (1) pop rd pop register from stack rd ? stack none 2 (1) xch z, rd exchange ram location te m p rd (z) ? ? ? rd, (z), te m p none 2 las z, rd load and set ram location te m p rd (z) ? ? ? rd, (z), te m p v ( z ) none 2 lac z, rd load and clear ram location te m p rd (z) ? ? ? rd, (z), ($ffh ? rd) ? (z) none 2 lat z, rd load and toggle ram location te m p rd (z) ? ? ? rd, (z), te m p ? (z) none 2 bit and bit-test instructions lsl rd logical shift left rd(n+1) rd(0) c ? ? ? rd(n), 0, rd(7) z,c,n,v,h 1 lsr rd logical shift right rd(n) rd(7) c ? ? ? rd(n+1), 0, rd(0) z,c,n,v 1 rol rd rotate left through carry rd(0) rd(n+1) c ? ? ? c, rd(n), rd(7) z,c,n,v,h 1 ror rd rotate right through carry rd(7) rd(n) c ? ? ? c, rd(n+1), rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) ? rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) ? rd(7..4) none 1 bset s flag set sreg(s) ? 1 sreg(s) 1 bclr s flag clear sreg(s) ? 0 sreg(s) 1 sbi a, b set bit in i/o register i/o(a, b) ? 1 none 1 cbi a, b clear bit in i/o register i/o(a, b) ? 0 none 1 bst rr, b bit store from register to t t ? rr(b) t 1 bld rd, b bit load from t to register rd(b) ? t none 1 sec set carry c ? 1 c 1 clc clear carry c ? 0 c 1 sen set negative flag n ? 1 n 1 cln clear negative flag n ? 0 n 1 sez set zero flag z ? 1 z 1 clz clear zero flag z ? 0 z 1 sei global interrupt enable i ? 1 i 1 cli global interrupt disable i ? 0 i 1 ses set signed test flag s ? 1 s 1 cls clear signed test flag s ? 0 s 1 mnemonics operands description operation flags #clocks
66 xmega a4u [datasheet] 8387d?avr?02/2013 notes: 1. cycle times for data memory accesses assume internal memo ry accesses, and are not valid for accesses via the external r am interface. 2. one extra cycle must be added when accessing internal sram. sev set two?s complement overflow v ? 1 v 1 clv clear two?s complement overflow v ? 0 v 1 set set t in sreg t ? 1 t 1 clt clear t in sreg t ? 0 t 1 seh set half carry flag in sreg h ? 1 h 1 clh clear half carry flag in sreg h ? 0 h 1 mcu control instructions break break (see specific descr. for break) none 1 nop no operation none 1 sleep sleep (see specific descr. for sleep) none 1 wdr watchdog reset (see specific descr. for wdr) none 1 mnemonics operands description operation flags #clocks
67 xmega a4u [datasheet] 8387d?avr?02/2013 35. packaging information 35.1 44a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10mm body size, 1.0mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) c 44a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
68 xmega a4u [datasheet] 8387d?avr?02/2013 35.2 pw
69 xmega a4u [datasheet] 8387d?avr?02/2013 35.3 44m1 title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 44m1 zws h 44m1, 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 9/26/08 common dimensions (unit of measure = mm) symbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 a3 0.20 ref b 0.18 0.23 0.30 d d2 5.00 5.20 5.40 6.90 7.00 7.10 6.90 7.00 7.10 e e2 5.00 5.20 5.40 e 0.50 bsc l 0.59 0.64 0.69 k 0.20 0.26 0.41 note: jedec standard mo-220, fig. 1 (saw singulation) vkkd-3. top view side view bottom view d e marked pin# 1 id e2 d2 b e pin #1 corner l a1 a3 a seating plane pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 1 2 3
70 xmega a4u [datasheet] 8387d?avr?02/2013 35.4 49c2 title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 49c2 cbd a 49c2, 49-ball (7 x 7 array), 0.65mm pitch, 5.0 x 5.0 x 1.0mm, very thin, fine-pitch ball grid array package (vfbga) 3/14/08 common dimensions (unit of measure = mm) symbol min nom max note a ? ? 1.00 a1 0.20 ? ? a2 0.65 ? ? d 4.90 5.00 5.10 d1 3.90 bsc e 4.90 5.00 5.10 e1 3.90 bsc b 0.30 0.35 0.40 e 0.65 bsc top view side view a1 ball id g f e d c b a 1 2 3 4 5 6 7 a a1 a2 d e 0.10 e1 d1 49 - ? 0.35 0.05 e a1 ball corner bottom view b e
71 xmega a4u [datasheet] 8387d?avr?02/2013 36. electrical characteristics all typical values are measured at t = 25 ? c unless other temperature condition is given. all minimum and maximum values are valid across operating temperatur e and voltage unless other conditions are given. 36.1 atxmega16a4u 36.1.1 absolute maximum ratings stresses beyond those listed in table 36-1 may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. table 36-1. absolute maximum ratings. 36.1.2 general operating ratings the device must operate within the ratings listed in table 36-2 in order for all other electr ical characteristics and typical characteristics of the device to be valid. table 36-2. general operating conditions. symbol parameter condition min. typ. max. units v cc power supply voltage -0.3 4 v i vcc current into a v cc pin 200 ma i gnd current out of a gnd pin 200 ma v pin pin voltage with respect to gnd and v cc -0.5 v cc +0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 c symbol parameter condition min. typ. max. units v cc power supply voltage 1.60 3.6 v av cc analog supply voltage 1.60 3.6 v t a temperature range -40 85 c t j junction temperature -40 105 c
72 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-3. operating voltage and frequency. the maximum cpu clock frequency depends on v cc . as shown in figure 36-1 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. figure 36-1. maximum frequency vs. v cc . symbol parameter condition min. typ. max. units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32 1.8 12 32 mhz v 2.7 3.6 1.6 safe operating area
73 xmega a4u [datasheet] 8387d?avr?02/2013 36.1.3 current consumption table 36-4. current consumption for active mode and sleep modes. notes: 1. all power reduction registers set. 2. maximum limits are based on characterization, and not tested in production . symbol parameter condition min. typ. max. units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 40 a v cc = 3.0v 80 1mhz, ext. clk v cc = 1.8v 230 v cc = 3.0v 480 2mhz, ext. clk v cc = 1.8v 430 600 v cc = 3.0v 0.9 1.4 ma 32mhz, ext. clk 9.6 12 idle power consumption (1) 32khz, ext. clk v cc = 1.8v 2.4 a v cc = 3.0v 3.9 1mhz, ext. clk v cc = 1.8v 62 v cc = 3.0v 118 2mhz, ext. clk v cc = 1.8v 125 225 v cc = 3.0v 240 350 32mhz, ext. clk 3.8 5.5 ma power-down power consumption t=25c v cc = 3.0v 0.1 1.0 a t=85c 1.2 4.5 wdt and sampled bod enabled, t=25c v cc = 3.0v 1.3 3.0 wdt and sampled bod enabled, t = 85c 2.4 6.0 power-save power consumption (2) rtc from ulp clock, wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.2 a v cc = 3.0v 1.3 rtc from 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.6 2.0 v cc = 3.0v 0.7 2.0 rtc from low power 32.768khz tosc, t = 25c v cc = 1.8v 0.8 3.0 v cc = 3.0v 1.0 3.0 reset power consumption current through reset pin substracted v cc = 3.0v 320 a
74 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-5. current consumption for modules and peripherals. note: 1. all parameters measured as the difference in current consumption between module enabled and disabled. all data at v cc = 3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditions are given. symbol parameter condition (1) min. typ. max. units i cc ulp oscillator 1.0 a 32.768khz int. oscillator 27 a 2mhz int. oscillator 85 a dfll enabled with 32.768khz int. osc. as reference 115 32mhz int. oscillator 270 a dfll enabled with 32.768khz int. osc. as reference 460 pll 20x multiplication factor, 32mhz int. osc. div4 as reference 220 a watchdog timer 1.0 a bod continuous mode 138 a sampled mode, includes ulp oscillator 1.2 internal 1.0v reference 100 a temperature sensor 95 a adc 250ksps v ref = ext ref 3.0 ma currlimit = low 2.6 currlimit = medium 2.1 currlimit = high 1.6 dac 250ksps v ref = ext ref no load normal mode 1.9 ma low power mode 1.1 ac high speed mode 330 a low power mode 130 dma 615kbps between i/o registers and sram 108 a timer/counter 16 a usart rx and tx enabled, 9600 baud 2.5 a flash memory and eeprom programming 4.0 8.0 ma
75 xmega a4u [datasheet] 8387d?avr?02/2013 36.1.4 wake-up time from sleep modes table 36-6. device wake-up time from slee p modes with various system clock sources. note: 1. the wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see figure 36-2 . all peripherals and modules start execution from the first clock cycle, ex pect the cpu that is halted for four cloc k cycles before program execution starts. figure 36-2. wake-up time definition. symbol parameter condition min. typ. (1) max. units t wakeup wake-up time from idle, standby, and extended standby mode external 2mhz clock 2.0 s 32.768khz internal oscillator 120 2mhz internal oscillator 2.0 32mhz internal oscillator 0.2 wake-up time from power-save and power-down mode external 2mhz clock 4.5 32.768khz internal oscillator 320 2mhz internal oscillator 9.0 32mhz internal oscillator 5.0 wakeup request clock output wakeup time
76 xmega a4u [datasheet] 8387d?avr?02/2013 36.1.5 i/o pin characteristics the i/o pins comply with the jedec lv ttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. table 36-7. i/o pin characteristics. notes: 1. the sum of all i oh for porta and portb must not exceed 100ma. the sum of all i oh for portc must not exceed 200ma. the sum of all i oh for portd and pins pe[0-1] on porte must not exceed 200ma. the sum of all i oh for pe[2-3] on porte, portr and pdi must not exceed 100ma. 2. the sum of all i ol for porta and portb must not exceed 100ma. the sum of all i ol for portc must not not exceed 200ma. the sum of all i ol for portd and pins pe[0-1] on porte must not exceed 200ma. the sum of all i ol for pe[2-3] on porte, portr and pdi must not exceed 100ma. symbol parameter condition min. typ. max. units i oh (1) / i ol (2) i/o pin source/sink current -20 20 ma v ih high level input voltage v cc = 2.7 - 3.6v 2.0 v cc +0.3 v v cc = 2.0 - 2.7v 0.7*v cc v cc +0.3 v cc = 1.6 - 2.0v 0.8*v cc v cc +0.3 v il low level input voltage v cc = 2.7- 3.6v -0.3 0.8 v v cc = 2.0 - 2.7v -0.3 0.3*v cc v cc = 1.6 - 2.0v -0.3 0.2*v cc v oh high level output voltage v cc = 3.0 - 3.6v i oh = -2ma 2.4 0.94*v cc v v cc = 2.3 - 2.7v i oh = -1ma 2.0 0.96*v cc i oh = -2ma 1.7 0.92*v cc v cc = 3.3v i oh = -8ma 2.6 2.9 v cc = 3.0v i oh = -6ma 2.1 2.6 v cc = 1.8v i oh = -2ma 1.4 1.6 v ol low level output voltage v cc = 3.0 - 3.6v i ol = 2ma 0.05*v cc 0.4 v v cc = 2.3 - 2.7v i ol = 1ma 0.03*v cc 0.4 i ol = 2ma 0.06*v cc 0.7 v cc = 3.3v i ol = 15ma 0.4 0.76 v cc = 3.0v i ol = 10ma 0.3 0.64 v cc = 1.8v i ol = 5ma 0.2 0.46 i in input leakage current t = 25c <0.01 0.1 a r p pull/buss keeper resistor 24 k ? t r rise time no load 4.0 ns slew rate limitation 7.0
77 xmega a4u [datasheet] 8387d?avr?02/2013 36.1.6 adc characteristics table 36-8. power supply, reference and input range. table 36-9. clock and timing. symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1.0 av cc - 0.6 v r in input resistance switched 4.0 k ? c sample input capacitance switched 4.4 pf r aref reference input resistance (leakage only) >10 m ? c aref reference input capacitance static load 7.0 pf v in input range -0.1 av cc + 0.1 v conversion range differential mode, vinp - vinn -v ref v ref v conversion range single ended unsigned mode, vinp - ? v v ref - ? v v ? v fixed offset voltage 190 lsb symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 2000 khz measuring internal signals 100 125 f adc sample rate current limitation (currlimit) off 100 2000 ksps currlimit = low 100 1500 currlimit = medium 100 1000 currlimit = high 100 500 sampling time 1/2 clk adc cycle 0.25 5 s conversion time (latency) (res+2)/2+(gain !=0) res (resolution) = 8 or 12 5 8 clk adc cycles start-up time adc clock cycles 12 24 clk adc cycles adc settling time after changing reference or input mode 7 7 clk adc cycles after adc flush 1 1
78 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-10. accuracy characteristics. notes: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 5% to 95% input voltage range . 2. unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external v ref is used. table 36-11. gain stage characteristics. symbol parameter condition (2) min. typ. max. units res resolution programmable to 8 or 12 bit 8 12 12 bits inl (1) integral non-linearity 500ksps v cc -1.0v < v ref < v cc -0.6v 1.2 2.0 lsb all v ref 1.5 3.0 2000ksps v cc -1.0v < v ref < v cc -0.6v 1.0 2.0 all v ref 1.5 3.0 dnl (1) differential non-linearity guaranteed monotonic <0.8 <1.0 lsb offset error -1.0 mv temperature drift <0.01 mv/k operating voltage drift <0.6 mv/v gain error differential mode external reference -1.0 mv av cc /1.6 10 av cc /2.0 8.0 bandgap 5.0 temperature drift <0.02 mv/k operating voltage drift <0.5 mv/v noise differential mode, shorted input 2msps, v cc = 3.6v, clk per = 16mhz 0.4 mv rms symbol parameter condition min. typ. max. units r in input resistance switched in normal mode 4.0 k ? c sample input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 v cc - 0.6 v propagation delay adc conversion rate 1.0 clk adc cycles sample rate same as adc 100 1000 khz inl (1) integral non-linearity 500ksps all gain settings 1.5 4 lsb gain error 1x gain, normal mode -0.8 % 8x gain, normal mode -2.5 64x gain, normal mode -3.5
79 xmega a4u [datasheet] 8387d?avr?02/2013 note: 1. maximum numbers are based on characterisation and not test ed in production, and valid for 5% to 95% input voltage range. 36.1.7 dac characteristics table 36-12. power supply, reference and output range. table 36-13. clock and timing. offset error, input referred 1x gain, normal mode -2 mv 8x gain, normal mode -5 64x gain, normal mode -4 noise 1x gain, normal mode v cc = 3.6v ext. v ref 0.5 mv rms 8x gain, normal mode 1.5 64x gain, normal mode 11 symbol parameter condition min. typ. max. units symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v av ref external reference voltage 1.0 v cc - 0.6 v r channel dc output impedance 50 ? linear output voltage range 0.15 av cc -0.15 v r aref reference input resistance >10 m ? caref reference input capacitance static load 7 pf minimum resistance load 1.0 k ? maximum capacitance load 100 pf 1000 ? serial resistance 1.0 nf output sink/source operating within accuracy specification av cc /1000 ma safe operation 10 symbol parameter condition min. typ. max. units f dac conversion rate c load =100pf, maximum step size normal mode 0 1000 ksps low power mode 500
80 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-14. accuracy characteristics. note: 1. maximum numbers are based on charac terisation and not tested in production, and valid for 5% to 95% output voltage range . symbol parameter condition min. typ. max. units res input resolution 12 bits inl (1) integral non-linearity v ref = ext 1.0v v cc = 1.6v 2.0 3 lsb v cc = 3.6v 1.5 2.5 v ref =av cc v cc = 1.6v 2.0 4 v cc = 3.6v 1.5 4 v ref =int1v v cc = 1.6v 5.0 v cc = 3.6v 5.0 dnl (1) differential non-linearity v ref =ext 1.0v v cc = 1.6v 1.5 3.0 lsb v cc = 3.6v 0.6 1.5 v ref =av cc v cc = 1.6v 1.0 3.5 v cc = 3.6v 0.6 1.5 v ref =int1v v cc = 1.6v 4.5 v cc = 3.6v 4.5 gain error after calibration <4.0 lsb gain calibration step size 4.0 lsb gain calibration drift v ref = ext 1.0v <0.2 mv/k offset error after calibration <1.0 lsb offset calibration step size 1.0
81 xmega a4u [datasheet] 8387d?avr?02/2013 36.1.8 analog comparator characteristics table 36-15. analog comparator characteristics. 36.1.9 bandgap and internal 1.0v reference characteristics table 36-16. bandgap and internal 1.0v reference characteristics. symbol parameter condition min. typ. max. units v off input offset voltage <10 mv i lk input leakage current <1.0 na input voltage range -0.1 av cc v ac startup time 100 s v hys1 hysteresis, none 0 mv v hys2 hysteresis, small mode = high speed (hs) 13 mv mode = low power (lp) 30 v hys3 hysteresis, large mode = hs 30 mv mode = lp 60 t delay propagation delay v cc = 3.0v, t= 85c mode = hs 30 90 ns mode = hs 30 v cc = 3.0v, t= 85c mode = lp 130 500 mode = lp 130 64-level voltage scaler integral non-linearity (inl) 0.3 0.5 lsb symbol parameter condition min. typ. max. units startup time as reference for adc or dac 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t= 85c, after calibration 0.99 1.0 1.01 v variation over voltage and temperature relative to t= 85c, v cc = 3.0v 1.5 %
82 xmega a4u [datasheet] 8387d?avr?02/2013 36.1.10 brownout detection characteristics table 36-17. brownout detection characteristics. 36.1.11 external reset characteristics table 36-18. external reset characteristics. 36.1.12 power-on reset characteristics table 36-19. power-on reset characteristics. note: 1. v pot- values are only valid when bod is disabled. when bod is enabled v pot- = v pot+ . symbol parameter condition min. typ. max. units v bot bod level 0 falling v cc 1.60 1.62 1.72 v bod level 1 falling v cc 1.8 bod level 2 falling v cc 2.0 bod level 3 falling v cc 2.2 bod level 4 falling v cc 2.4 bod level 5 falling v cc 2.6 bod level 6 falling v cc 2.8 bod level 7 falling v cc 3.0 t bod detection time continuous mode 0.4 s sampled mode 1000 v hyst hysteresis 1.2 % symbol parameter condition min. typ. max. units t ext minimum reset pulse width 95 1000 ns v rst reset threshold voltage (v ih ) v cc = 2.7 - 3.6v 0.60v cc v v cc = 1.6 - 2.7v 0.60v cc reset threshold voltage (v il ) v cc = 2.7 - 3.6v 0.50v cc v cc = 1.6 - 2.7v 0.40v cc r rst reset pin pull-up resistor 25 k ? symbol parameter condition min. typ. max. units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.0 v pot+ por threshold voltage rising v cc 1.3 1.59 v
83 xmega a4u [datasheet] 8387d?avr?02/2013 36.1.13 flash and eeprom memory characteristics table 36-20. endurance and data retention. table 36-21. progr amming time. notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. 36.1.14 clock and oscillator characteristics 36.1.14.1calibrated 32.768khz internal oscillator characteristics table 36-22. 32.768khz internal oscillator characteristics. symbol parameter condition min. typ. max. units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 80k cycle 85c 30k data retention 25c 100 year 55c 25 symbol parameter condition min. typ. (1) max. units chip erase 16kb flash, eeprom (2) and sram erase 45 ms application erase section erase 6 ms flash page erase 4 ms page write 4 atomic page erase and write 8 eeprom page erase 4 ms page write 4 atomic page erase and write 8 symbol parameter condition min. typ. max. units frequency 32.768 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 %
84 xmega a4u [datasheet] 8387d?avr?02/2013 36.1.14.2calibrated 2mhz rc internal oscillator characteristics table 36-23. 2mhz internal oscillator characteristics. 36.1.14.3calibrated and tunable 32mhz in ternal oscillator characteristics table 36-24. 32mhz internal oscillator characteristics. 36.1.14.432khz internal ulp oscillator characteristics table 36-25. 32khz internal ulp oscillator characteristics. symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.2 mhz factory calibrated frequency 2.0 mhz factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 % dfll calibration stepsize 0.21 % symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 30 55 mhz factory calibrated frequency 32 mhz factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 % dfll calibration step size 0.22 % symbol parameter condition min. typ. max. units output frequency 32 khz accuracy -30 30 %
85 xmega a4u [datasheet] 8387d?avr?02/2013 36.1.14.5internal phase locked l oop (pll) characteristics table 36-26. internal pll characteristics. note: 1. the maximum output frequency vs. supply voltage is linear be tween 1.8v and 2.7v, and can never be higher than four times the maximum cpu frequency. 36.1.14.6external clock characteristics figure 36-3. external clock drive waveform table 36-27. external clock used as system clock without prescaling. note: 1. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. symbo l parameter condition min. typ. max. units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.6 - 1.8v 20 48 mhz v cc = 2.7 - 3.6v 20 128 start-up time 25 s re-lock time 25 s t ch t cl t ck t ch v il1 v ih1 t cr t cf symbol parameter condition min. typ. max. units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 ? t ck change in period from one clock cycle to the next 10 %
86 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-28. external clock with prescaler (1) for system clock. notes: 1. system clock prescale rs must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. 36.1.14.7external 16mhz crystal o scillator and xosc characteristic table 36-29. external 16mhz crystal oscillator and xosc characteristics. symbol parameter condition min. typ. max. units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 ? t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units cycle to cycle jitter xoscpwr=0 frqrange=0 <10 ns frqrange=1, 2, or 3 <1.0 xoscpwr=1 <1.0 long term jitter xoscpwr=0 frqrange=0 <6.0 ns frqrange=1, 2, or 3 <0.5 xoscpwr=1 <0.5 frequency error xoscpwr=0 frqrange=0 <0.1 % frqrange=1 <0.05 frqrange=2 or 3 <0.005 xoscpwr=1 <0.005
87 xmega a4u [datasheet] 8387d?avr?02/2013 duty cycle xoscpwr=0 frqrange=0 40 % frqrange=1 42 frqrange=2 or 3 45 xoscpwr=1 48 r q negative impedance (1) xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 2.4k ? 1mhz crystal, cl=20pf 8.7k 2mhz crystal, cl=20pf 2.1k xoscpwr=0, frqrange=1, cl=20pf 2mhz crystal 4.2k 8mhz crystal 250 9mhz crystal 195 xoscpwr=0, frqrange=2, cl=20pf 8mhz crystal 360 9mhz crystal 285 12mhz crystal 155 xoscpwr=0, frqrange=3, cl=20pf 9mhz crystal 365 12mhz crystal 200 16mhz crystal 105 xoscpwr=1, frqrange=0, cl=20pf 9mhz crystal 435 12mhz crystal 235 16mhz crystal 125 xoscpwr=1, frqrange=1, cl=20pf 9mhz crystal 495 12mhz crystal 270 16mhz crystal 145 xoscpwr=1, frqrange=2, cl=20pf 12mhz crystal 305 16mhz crystal 160 xoscpwr=1, frqrange=3, cl=20pf 12mhz crystal 380 16mhz crystal 205 esr sf = safety factor min(r q )/sf k ? c xtal1 parasitic capacitance xtal1 pin 5.4 pf c xtal2 parasitic capacitance xtal2 pin 7.1 pf c load parasitic capacitance load 3.07 pf symbol parameter condition min. typ. max. units
88 xmega a4u [datasheet] 8387d?avr?02/2013 note: 1. numbers for negative impedance are not tested in production but guaranteed from design and characterization. 36.1.14.8external 32.768khz crystal o scillator and tosc characteristics table 36-30. external 32.768khz crystal o scillator and tosc characteristics. note: 1. see figure 36-4 for definition. figure 36-4. tosc input capacitance. the parasitic capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. symbol parameter condition min. typ. max. units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k ? crystal load capacitance 9.0pf 35 c tosc1 parasitic capacitance tosc1 pin 5.4 pf alternate tosc location 4.0 c tosc2 parasitic capacitance tosc2 pin 7.1 pf alternate tosc location 4.0 recommended safety factor capacitance load matched to crystal specification 3 c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal
89 xmega a4u [datasheet] 8387d?avr?02/2013 36.1.15 spi characteristics figure 36-5. spi timing requirements in master mode. figure 36-6. spi timing requirements in slave mode. msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
90 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-31. spi timing characteristics and requirements. 36.1.16 two-wire interf ace characteristics table 36-32 on page 91 describes the requirements for devices connected to the two-wire interface bus. the atmel avr xmega two-wire interface meets or exceeds thes e requirements under the noted conditions. timing symbols refer to figure 36-7 on page 90 . figure 36-7. two-wire interface bus timing. symbol parameter condition min. typ. max. units t sck sck period master (see table 21-4 in xmega au manual) ns t sckw sck high/low width master 0.5*sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 10 t mih miso hold after sck master 10 t mos mosi setup sck master 0.5*sck t moh mosi hold after sck master 1 t ssck slave sck period slave 4t clk per t ssckw sck high/low width slave 2t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3 t sih mosi hold after sck slave tclk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8 t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto
91 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-32. two-wire interface characteristics. notes: 1. required only for f scl > 100khz. 2. c b = capacitance of one bus line in pf. 3. f per = peripheral clock frequency. symbol parameter condition min. typ. max. units v ih input high voltage 0.7*v cc v cc +0.5 v v il input low voltage 0.5 0.3*v cc v v hys hysteresis of schmitt trigger inputs 0.05*v cc (1) v v ol output low voltage 3ma, sink current 0 0.4 v t r rise time for both sda and scl 20+0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20+0.1c b (1)(2) 250 ns t sp spikes suppressed by input filter 0 50 ns i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 10 pf f scl scl clock frequency f per (3) >max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl ? 100khz ? f scl > 100khz t hd;sta hold time (repeated) start condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl ? 100khz 4.7 s f scl > 100khz 1.3 t high high period of scl clock f scl ? 100khz 4.0 s f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl ? 100khz 4.7 s f scl > 100khz 0.6 t hd;dat data hold time f scl ? 100khz 0 3.45 s f scl > 100khz 0 0.9 t su;dat data setup time f scl ? 100khz 250 s f scl > 100khz 100 t su;sto setup time for stop condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl ? 100khz 4.7 s f scl > 100khz 1.3 v cc 0.4 v ? 3 ma --------------------------- - 100 ns c b -------------- - 300 ns c b -------------- -
92 xmega a4u [datasheet] 8387d?avr?02/2013 36.2 atxmega32a4u 36.2.1 absolute maximum ratings stresses beyond those listed in table 36-33 may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. table 36-33. absolute maximum ratings. 36.2.2 general operating ratings the device must operate within the ratings listed in table 36-34 in order for all other electrical characteristics and typical characteristics of the device to be valid. table 36-34. general operating conditions. table 36-35. operating voltage and frequency. symbol parameter condition min. typ. max. units v cc power supply voltage -0.3 4 v i vcc current into a v cc pin 200 ma i gnd current out of a gnd pin 200 ma v pin pin voltage with respect to gnd and v cc -0.5 v cc +0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 c symbol parameter condition min. typ. max. units v cc power supply voltage 1.60 3.6 v av cc analog supply voltage 1.60 3.6 v t a temperature range -40 85 c t j junction temperature -40 105 c symbol parameter condition min. typ. max. units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32
93 xmega a4u [datasheet] 8387d?avr?02/2013 the maximum cpu clock frequency depends on v cc . as shown in figure 36-8 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. figure 36-8. maximum frequency vs. v cc . 1.8 12 32 mhz v 2.7 3.6 1.6 safe operating area
94 xmega a4u [datasheet] 8387d?avr?02/2013 36.2.3 current consumption table 36-36. current consumption for active mode and sleep modes. notes: 1. all power reduction registers set. 2. maximum limits are based on characterization, and not tested in production. symbol parameter condition min. typ. max. units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 40 a v cc = 3.0v 80 1mhz, ext. clk v cc = 1.8v 230 v cc = 3.0v 480 2mhz, ext. clk v cc = 1.8v 430 600 v cc = 3.0v 0.9 1.4 ma 32mhz, ext. clk 9.6 12 idle power consumption (1) 32khz, ext. clk v cc = 1.8v 2.4 a v cc = 3.0v 3.9 1mhz, ext. clk v cc = 1.8v 62 v cc = 3.0v 118 2mhz, ext. clk v cc = 1.8v 125 225 v cc = 3.0v 240 350 32mhz, ext. clk 3.8 5.5 ma power-down power consumption t=25c v cc = 3.0v 0.1 1.0 a t=85c 1.2 4.5 wdt and sampled bod enabled, t=25c v cc = 3.0v 1.3 3.0 wdt and sampled bod enabled, t = 85c 2.4 6.0 power-save power consumption (2) rtc from ulp clock, wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.2 a v cc = 3.0v 1.3 rtc from 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.6 2.0 v cc = 3.0v 0.7 2.0 rtc from low power 32.768khz tosc, t = 25c v cc = 1.8v 0.8 3.0 v cc = 3.0v 1.0 3.0 reset power consumption current through reset pin substracted v cc = 3.0v 320
95 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-37. current consumption for modules and peripherals. note: 1. all parameters measured as the difference in current consumption between module enabled and disabled. all data at v cc = 3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditions are given. symbol parameter condition (1) min. typ. max. units i cc ulp oscillator 1.0 a 32.768khz int. oscillator 27 a 2mhz int. oscillator 85 a dfll enabled with 32.768khz int. osc. as reference 115 32mhz int. oscillator 270 a dfll enabled with 32.768khz int. osc. as reference 460 pll 20x multiplication factor, 32mhz int. osc. div4 as reference 220 a watchdog timer 1.0 a bod continuous mode 138 a sampled mode, includes ulp oscillator 1.2 internal 1.0v reference 100 a temperature sensor 95 a adc 250ksps v ref = ext ref 3.0 ma currlimit = low 2.6 currlimit = medium 2.1 currlimit = high 1.6 dac 250ksps v ref = ext ref no load normal mode 1.9 ma low power mode 1.1 ac high speed mode 330 a low power mode 130 dma 615kbps between i/o registers and sram 108 a timer/counter 16 a usart rx and tx enabled, 9600 baud 2.5 a flash memory and eeprom programming 4.0 8.0 ma
96 xmega a4u [datasheet] 8387d?avr?02/2013 36.2.4 wake-up time from sleep modes table 36-38. device wake-up time from slee p modes with various system clock sources. note: 1. the wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see figure 36-9 . all peripherals and modules start execution from the first clock cycle, ex pect the cpu that is halted for four cloc k cycles before program execution starts. figure 36-9. wake-up time definition. symbol parameter condition min. typ. (1) max. units t wakeup wake-up time from idle, standby, and extended standby mode external 2mhz clock 2.0 s 32.768khz internal oscillator 120 2mhz internal oscillator 2.0 32mhz internal oscillator 0.2 wake-up time from power-save and power-down mode external 2mhz clock 4.5 s 32.768khz internal oscillator 320 2mhz internal oscillator 9.0 32mhz internal oscillator 5.0 wakeup request clock output wakeup time
97 xmega a4u [datasheet] 8387d?avr?02/2013 36.2.5 i/o pin characteristics the i/o pins comply with the jedec lv ttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. table 36-39. i/o pin characteristics. notes: 1. the sum of all i oh for porta and portb must not exceed 100ma. the sum of all i oh for portc must not exceed 200ma. the sum of all i oh for portd and pins pe[0-1] on porte must not exceed 200ma. the sum of all i oh for pe[2-3] on porte, portr and pdi must not exceed 100ma. 2. the sum of all i ol for porta and portb must not exceed 100ma. the sum of all i ol for portc must not not exceed 200ma. the sum of all i ol for portd and pins pe[0-1] on porte must not exceed 200ma. the sum of all i ol for pe[2-3] on porte, portr and pdi must not exceed 100ma. symbol parameter condition min. typ. max. units i oh (1) / i ol (2) i/o pin source/sink current -20 20 ma v ih high level input voltage v cc = 2.7 - 3.6v 2.0 v cc +0.3 v v cc = 2.0 - 2.7v 0.7*v cc v cc +0.3 v cc = 1.6 - 2.0v 0.8*v cc v cc +0.3 v il low level input voltage v cc = 2.7- 3.6v -0.3 0.8 v v cc = 2.0 - 2.7v -0.3 0.3*v cc v cc = 1.6 - 2.0v -0.3 0.2*v cc v oh high level output voltage v cc = 3.0 - 3.6v i oh = -2ma 2.4 0.94*v cc v v cc = 2.3 - 2.7v i oh = -1ma 2.0 0.96*v cc i oh = -2ma 1.7 0.92*v cc v cc = 3.3v i oh = -8ma 2.6 2.9 v cc = 3.0v i oh = -6ma 2.1 2.6 v cc = 1.8v i oh = -2ma 1.4 1.6 v ol low level output voltage v cc = 3.0 - 3.6v i ol = 2ma 0.05*v cc 0.4 v v cc = 2.3 - 2.7v i ol = 1ma 0.03*v cc 0.4 i ol = 2ma 0.06*v cc 0.7 v cc = 3.3v i ol = 15ma 0.4 0.76 v cc = 3.0v i ol = 10ma 0.3 0.64 v cc = 1.8v i ol = 5ma 0.2 0.46 i in input leakage current t = 25c <0.01 0.1 a r p pull/buss keeper resistor 24 k ? t r rise time no load 4.0 ns slew rate limitation 7.0
98 xmega a4u [datasheet] 8387d?avr?02/2013 36.2.6 adc characteristics table 36-40. power supply, reference and input range. table 36-41. clock and timing. symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1 av cc - 0.6 v r in input resistance switched 4.0 k ? c sample input capacitance switched 4.4 pf r aref reference input resistance (leakage only) >10 m ? c aref reference input capacitance static load 7 pf v in input range -0.1 av cc + 0.1 v conversion range differential mode, vinp - vinn -v ref v ref v conversion range single ended unsigned mode, vinp - ? v v ref - ? v v ? v fixed offset voltage 190 lsb symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 2000 khz measuring internal signals 100 125 f adc sample rate current limitation (currlimit) off 100 2000 ksps currlimit = low 100 1500 currlimit = medium 100 1000 currlimit = high 100 500 sampling time 1/2 clk adc cycle 0.25 5 s conversion time (latency) (res+2)/2+(gain !=0) res (resolution) = 8 or 12 5 8 clk adc cycles start-up time adc clock cycles 12 24 clk adc cycles adc settling time after changing reference or input mode 7 7 clk adc cycles after adc flush 1 1
99 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-42. accuracy characteristics. notes: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 5% to 95% input voltage range . 2. unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external v ref is used. table 36-43. gain stage characteristics. symbol parameter condition (2) min. typ. max. units res resolution programmable to 8 or 12 bit 8 12 12 bits inl (1) integral non-linearity 500ksps v cc -1.0v < v ref < v cc -0.6v 1.2 2.0 lsb all v ref 1.5 3.0 2000ksps v cc -1.0v < v ref < v cc -0.6v 1.0 2.0 all v ref 1.5 3.0 dnl (1) differential non-linearity guaranteed monotonic <0.8 <1.0 lsb offset error -1.0 mv temperature drift <0.01 mv/k operating voltage drift <0.6 mv/v gain error differential mode external reference -1.0 mv av cc /1.6 10 av cc /2.0 8.0 bandgap 5.0 temperature drift <0.02 mv/k operating voltage drift <0.5 mv/v noise differential mode, shorted input 2msps, v cc = 3.6v, clk per = 16mhz 0.4 mv rms symbol parameter condition min. typ. max. units r in input resistance switched in normal mode 4.0 k ? c sample input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 v cc - 0.6 v propagation delay adc conversion rate 1.0 clk adc cycles sample rate same as adc 100 1000 khz inl (1) integral non-linearity 500ksps all gain settings 1.5 4.0 lsb gain error 1x gain, normal mode -0.8 % 8x gain, normal mode -2.5 64x gain, normal mode -3.5
100 xmega a4u [datasheet] 8387d?avr?02/2013 note: 1. maximum numbers are based on characterisation and not test ed in production, and valid for 5% to 95% input voltage range. 36.2.7 dac characteristics table 36-44. power supply, reference and output range. table 36-45. clock and timing. offset error, input referred 1x gain, normal mode -2.0 mv 8x gain, normal mode -5.0 64x gain, normal mode -4.0 noise 1x gain, normal mode v cc = 3.6v ext. v ref 0.5 mv rms 8x gain, normal mode 1.5 64x gain, normal mode 11 symbol parameter condition min. typ. max. units symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v av ref external reference voltage 1.0 v cc - 0.6 v r channel dc output impedance 50 ? linear output voltage range 0.15 av cc -0.15 v r aref reference input resistance >10 m ? caref reference input capacitance static load 7.0 pf minimum resistance load 1.0 k ? maximum capacitance load 100 pf 1000 ? serial resistance 1.0 nf output sink/source operating within accuracy specification av cc /1000 ma safe operation 10 symbol parameter condition min. typ. max. units f dac conversion rate c load =100pf, maximum step size normal mode 0 1000 ksps low power mode 500
101 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-46. accuracy characteristics. note: 1. maximum numbers are based on charac terisation and not tested in production, and valid for 5% to 95% output voltage range . symbol parameter condition min. typ. max. units res input resolution 12 bits inl (1) integral non-linearity v ref = ext 1.0v v cc = 1.6v 2.0 3.0 lsb v cc = 3.6v 1.5 2.5 v ref =av cc v cc = 1.6v 2.0 4.0 v cc = 3.6v 1.5 4.0 v ref =int1v v cc = 1.6v 5.0 v cc = 3.6v 5.0 dnl (1) differential non-linearity v ref =ext 1.0v v cc = 1.6v 1.5 3.0 lsb v cc = 3.6v 0.6 1.5 v ref =av cc v cc = 1.6v 1.0 3.5 v cc = 3.6v 0.6 1.5 v ref =int1v v cc = 1.6v 4.5 v cc = 3.6v 4.5 gain error after calibration <4.0 lsb gain calibration step size 4.0 lsb gain calibration drift v ref = ext 1.0v <0.2 mv/k offset error after calibration <1.0 lsb offset calibration step size 1.0
102 xmega a4u [datasheet] 8387d?avr?02/2013 36.2.8 analog comparator characteristics table 36-47. analog comparator characteristics. 36.2.9 bandgap and internal 1.0v reference characteristics table 36-48. bandgap and internal 1.0v reference characteristics. symbol parameter condition min. typ. max. units v off input offset voltage <10 mv i lk input leakage current <1 na input voltage range -0.1 av cc v ac startup time 100 s v hys1 hysteresis, none 0 mv v hys2 hysteresis, small mode = high speed (hs) 13 mv mode = low power (lp) 30 v hys3 hysteresis, large mode = hs 30 mv mode = lp 60 t delay propagation delay v cc = 3.0v, t= 85c mode = hs 30 90 ns mode = hs 30 v cc = 3.0v, t= 85c mode = lp 130 500 mode = lp 130 64-level voltage scaler integral non-linearity (inl) 0.3 0.5 lsb symbol parameter condition min. typ. max. units startup time as reference for adc or dac 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t= 85c, after calibration 0.99 1.0 1.01 v variation over voltage and temperature relative to t= 85c, v cc = 3.0v 1.5 %
103 xmega a4u [datasheet] 8387d?avr?02/2013 36.2.10 brownout detection characteristics table 36-49. brownout detection characteristics. 36.2.11 external reset characteristics table 36-50. external reset characteristics. 36.2.12 power-on reset characteristics table 36-51. power-on reset characteristics. note: 1. v pot- values are only valid when bod is disabled. when bod is enabled v pot- = v pot+ . symbol parameter condition min. typ. max. units v bot bod level 0 falling v cc 1.60 1.62 1.72 v bod level 1 falling v cc 1.8 bod level 2 falling v cc 2.0 bod level 3 falling v cc 2.2 bod level 4 falling v cc 2.4 bod level 5 falling v cc 2.6 bod level 6 falling v cc 2.8 bod level 7 falling v cc 3.0 t bod detection time continuous mode 0.4 s sampled mode 1000 v hyst hysteresis 1.2 % symbol parameter condition min. typ. max. units t ext minimum reset pulse width 95 1000 ns v rst reset threshold voltage (v ih ) v cc = 2.7 - 3.6v 0.60*v cc v v cc = 1.6 - 2.7v 0.60*v cc reset threshold voltage (v il ) v cc = 2.7 - 3.6v 0.50*v cc v cc = 1.6 - 2.7v 0.40*v cc r rst reset pin pull-up resistor 25 k ? symbol parameter condition min. typ. max. units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.0 v pot+ por threshold voltage rising v cc 1.3 1.59 v
104 xmega a4u [datasheet] 8387d?avr?02/2013 36.2.13 flash and eeprom memory characteristics table 36-52. endurance and data retention. table 36-53. progr amming time. notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. 36.2.14 clock and oscillator characteristics 36.2.14.1calibrated 32.768khz internal oscillator characteristics table 36-54. 32.768khz internal oscillator characteristics. symbol parameter condition min. typ. max. units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 80k cycle 85c 30k data retention 25c 100 year 55c 25 symbol parameter condition min. typ. (1) max. units chip erase 32kb flash, eeprom (2) and sram erase 50 ms application erase section erase 6 ms flash page erase 4 ms page write 4 atomic page erase and write 8 eeprom page erase 4 ms page write 4 atomic page erase and write 8 symbol parameter condition min. typ. max. units frequency 32.768 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 %
105 xmega a4u [datasheet] 8387d?avr?02/2013 36.2.14.2calibrated 2mhz rc internal oscillator characteristics table 36-55. 2mhz internal oscillator characteristics. 36.2.14.3calibrated and tunable 32mhz in ternal oscillator characteristics table 36-56. 32mhz internal oscillator characteristics. 36.2.14.432khz internal ulp oscillator characteristics table 36-57. 32khz internal ulp oscillator characteristics. symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.2 mhz factory calibrated frequency 2.0 mhz factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 % dfll calibration stepsize 0.21 % symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 30 55 mhz factory calibrated frequency 32 mhz factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 % dfll calibration step size 0.22 % symbol parameter condition min. typ. max. units output frequency 32 khz accuracy -30 30 %
106 xmega a4u [datasheet] 8387d?avr?02/2013 36.2.14.5internal phase locked l oop (pll) characteristics table 36-58. internal pll characteristics. note: 1. the maximum output frequency vs. supply voltage is linear be tween 1.8v and 2.7v, and can never be higher than four times the maximum cpu frequency. 36.2.14.6external clock characteristics figure 36-10.external clock drive waveform table 36-59. external clock used as system clock without prescaling. note: 1. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. symbo l parameter condition min. typ. max. units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.6 - 1.8v 20 48 mhz v cc = 2.7 - 3.6v 20 128 start-up time 25 s re-lock time 25 s t ch t cl t ck t ch v il1 v ih1 t cr t cf symbol parameter condition min. typ. max. units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 ? t ck change in period from one clock cycle to the next 10 %
107 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-60. external clock with prescaler (1) for system clock. notes: 1. system clock prescale rs must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. 36.2.14.7external 16mhz crystal o scillator and xosc characteristic table 36-61. external 16mhz crystal oscillator and xosc characteristics. symbol parameter condition min. typ. max. units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 ? t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units cycle to cycle jitter xoscpwr=0 frqrange=0 <10 ns frqrange=1, 2, or 3 <1 xoscpwr=1 <1 long term jitter xoscpwr=0 frqrange=0 <6 ns frqrange=1, 2, or 3 <0.5 xoscpwr=1 <0.5 frequency error xoscpwr=0 frqrange=0 <0.1 % frqrange=1 <0.05 frqrange=2 or 3 <0.005 xoscpwr=1 <0.005
108 xmega a4u [datasheet] 8387d?avr?02/2013 duty cycle xoscpwr=0 frqrange=0 40 % frqrange=1 42 frqrange=2 or 3 45 xoscpwr=1 48 r q negative impedance (1) xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 2.4k ? 1mhz crystal, cl=20pf 8.7k 2mhz crystal, cl=20pf 2.1k xoscpwr=0, frqrange=1, cl=20pf 2mhz crystal 4.2k 8mhz crystal 250 9mhz crystal 195 xoscpwr=0, frqrange=2, cl=20pf 8mhz crystal 360 9mhz crystal 285 12mhz crystal 155 xoscpwr=0, frqrange=3, cl=20pf 9mhz crystal 365 12mhz crystal 200 16mhz crystal 105 xoscpwr=1, frqrange=0, cl=20pf 9mhz crystal 435 12mhz crystal 235 16mhz crystal 125 xoscpwr=1, frqrange=1, cl=20pf 9mhz crystal 495 12mhz crystal 270 16mhz crystal 145 xoscpwr=1, frqrange=2, cl=20pf 12mhz crystal 305 16mhz crystal 160 xoscpwr=1, frqrange=3, cl=20pf 12mhz crystal 380 16mhz crystal 205 esr sf = safety factor min(r q )/sf k ? c xtal1 parasitic capacitance xtal1 pin 5.4 pf c xtal2 parasitic capacitance xtal2 pin 7.1 pf c load parasitic capacitance load 3.07 pf symbol parameter condition min. typ. max. units
109 xmega a4u [datasheet] 8387d?avr?02/2013 note: 1. numbers for negative impedance are not tested in production but guaranteed from design and characterization. 36.2.14.8external 32.768khz crystal o scillator and tosc characteristics table 36-62. external 32.768khz crystal o scillator and tosc characteristics. note: 1. see figure 36-11 for definition. figure 36-11.tosc input capacitance. the parasitic capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. symbol parameter condition min. typ. max. units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k ? crystal load capacitance 9.0pf 35 c tosc1 parasitic capacitance tosc1 pin 5.4 pf alternate tosc location 4.0 c tosc2 parasitic capacitance tosc2 pin 7.1 pf alternate tosc location 4.0 recommended safety factor capacitance load matched to crystal specification 3.0 c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal
110 xmega a4u [datasheet] 8387d?avr?02/2013 36.2.15 spi characteristics figure 36-12.spi timing requirements in master mode. figure 36-13.spi timing requirements in slave mode. msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
111 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-63. spi timing characteristics and requirements. symbol parameter condition min. typ. max. units t sck sck period master (see table 21-4 in xmega au manual) ns t sckw sck high/low width master 0.5sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 10 t mih miso hold after sck master 10 t mos mosi setup sck master 0.5sck t moh mosi hold after sck master 1.0 t ssck slave sck period slave 4t clk per t ssckw sck high/low width slave 2t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3.0 t sih mosi hold after sck slave tclk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8.0 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8.0
112 xmega a4u [datasheet] 8387d?avr?02/2013 36.2.16 two-wire interf ace characteristics table 36-64 describes the requirements for devices connected to the two-wire interface bus. the atmel avr xmega two-wire interface meets or exceeds these require ments under the noted conditions. timing symbols refer to figure 36- 14 . figure 36-14.two-wire interface bus timing. table 36-64. two-wire interface characteristics. t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto symbol parameter condition min. typ. max. units v ih input high voltage 0.7v cc v cc +0.5 v v il input low voltage 0.5 0.3v cc v v hys hysteresis of schmitt trigger inputs 0.05v cc (1) v v ol output low voltage 3ma, sink current 0 0.4 v t r rise time for both sda and scl 20+0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20+0.1c b (1)(2) 250 ns t sp spikes suppressed by input filter 0 50 ns i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 10 pf f scl scl clock frequency f per (3) >max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl ? 100khz ? f scl > 100khz t hd;sta hold time (repeated) start condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl ? 100khz 4.7 s f scl > 100khz 1.3 t high high period of scl clock f scl ? 100khz 4.0 s f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl ? 100khz 4.7 s f scl > 100khz 0.6 v cc 0.4 v ? 3 ma --------------------------- - 100 ns c b -------------- - 300 ns c b -------------- -
113 xmega a4u [datasheet] 8387d?avr?02/2013 notes: 1. required only for f scl > 100khz. 2. c b = capacitance of one bus line in pf. 3. f per = peripheral clock frequency. t hd;dat data hold time f scl ? 100khz 0 3.45 s f scl > 100khz 0 0.9 t su;dat data setup time f scl ? 100khz 250 s f scl > 100khz 100 t su;sto setup time for stop condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl ? 100khz 4.7 s f scl > 100khz 1.3 symbol parameter condition min. typ. max. units
114 xmega a4u [datasheet] 8387d?avr?02/2013 36.3 atxmega64a4u 36.3.1 absolute maximum ratings stresses beyond those listed in table 36-65 may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. table 36-65. absolute maximum ratings. 36.3.2 general operating ratings the device must operate within the ratings listed in table 36-66 in order for all other electrical characteristics and typical characteristics of the device to be valid. table 36-66. general operating conditions. table 36-67. operating voltage and frequency. symbol parameter condition min. typ. max. units v cc power supply voltage -0.3 4.0 v i vcc current into a v cc pin 200 ma i gnd current out of a gnd pin 200 ma v pin pin voltage with respect to gnd and v cc -0.5 v cc +0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 c symbol parameter condition min. typ. max. units v cc power supply voltage 1.60 3.6 v av cc analog supply voltage 1.60 3.6 v t a temperature range -40 85 c t j junction temperature -40 105 c symbol parameter condition min. typ. max. units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32
115 xmega a4u [datasheet] 8387d?avr?02/2013 the maximum cpu clock frequency depends on v cc . as shown in figure 36-15 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. figure 36-15.maximu m frequency vs. v cc . 1.8 12 32 mhz v 2.7 3.6 1.6 safe operating area
116 xmega a4u [datasheet] 8387d?avr?02/2013 36.3.3 current consumption table 36-68. current consumption for active mode and sleep modes. notes: 1. all power reduction registers set. 2. maximum limits are based on characterization, and not tested in production. symbol parameter condition min. typ. max. units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 52 a v cc = 3.0v 132 1mhz, ext. clk v cc = 1.8v 223 v cc = 3.0v 476 2mhz, ext. clk v cc = 1.8v 400 600 v cc = 3.0v 0.8 1.4 ma 32mhz, ext. clk 8.2 12 idle power consumption (1) 32khz, ext. clk v cc = 1.8v 2.4 a v cc = 3.0v 3.5 1mhz, ext. clk v cc = 1.8v 57 v cc = 3.0v 110 2mhz, ext. clk v cc = 1.8v 115 225 v cc = 3.0v 216 350 32mhz, ext. clk 3.5 5.5 ma power-down power consumption t=25c v cc = 3.0v 0.1 1.0 a t=85c 1.2 4.5 wdt and sampled bod enabled, t=25c v cc = 3.0v 1.4 3.0 wdt and sampled bod enabled, t = 85c 2.4 6.0 power-save power consumption (2) rtc from ulp clock, wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.2 a v cc = 3.0v 1.5 rtc from 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.6 2.0 v cc = 3.0v 0.7 2.0 rtc from low power 32.768khz tosc, t = 25c v cc = 1.8v 0.8 3.0 v cc = 3.0v 1.0 3.0 reset power consumption current through reset pin substracted v cc = 3.0v 140
117 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-69. current consumption for modules and peripherals. note: 1. all parameters measured as the difference in current consumption between module enabled and disabled. all data at v cc = 3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditions are given. symbol parameter condition (1) min. typ. max. units i cc ulp oscillator 1.0 a 32.768khz int. oscillator 29 a 2mhz int. oscillator 85 a dfll enabled with 32.768khz int. osc. as reference 120 32mhz int. oscillator 300 a dfll enabled with 32.768khz int. osc. as reference 465 pll 20x multiplication factor, 32mhz int. osc. div4 as reference 320 a watchdog timer 1.0 a bod continuous mode 138 a sampled mode, includes ulp oscillator 1.0 internal 1.0v reference 103 a temperature sensor 100 a adc 250ksps v ref = ext ref 3.0 ma currlimit = low 2.6 currlimit = medium 2.1 currlimit = high 1.6 dac 250ksps v ref = ext ref no load normal mode 1.9 ma low power mode 1.1 ac high speed mode 330 a low ppower mode 130 dma 615kbps between i/o registers and sram 108 a timer/counter 16 a usart rx and tx enabled, 9600 baud 2.5 a flash memory and eeprom programming 8.0 ma
118 xmega a4u [datasheet] 8387d?avr?02/2013 36.3.4 wake-up time from sleep modes table 36-70. device wake-up time from slee p modes with various system clock sources. note: 1. the wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see figure 36-16 . all peripherals and modules start execution from the first clock cycle, ex pect the cpu that is halted for four cloc k cycles before program execution starts. figure 36-16.wake-up time definition. symbol parameter condition min. typ. (1) max. units t wakeup wake-up time from idle, standby, and extended standby mode external 2mhz clock 2.0 s 32.768khz internal oscillator 120 2mhz internal oscillator 2.0 32mhz internal oscillator 0.2 wake-up time from power-save and power-down mode external 2mhz clock 4.5 s 32.768khz internal oscillator 320 2mhz internal oscillator 9.0 32mhz internal oscillator 4.0 wakeup request clock output wakeup time
119 xmega a4u [datasheet] 8387d?avr?02/2013 36.3.5 i/o pin characteristics the i/o pins comply with the jedec lv ttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. table 36-71. i/o pin characteristics. notes: 1. the sum of all i oh for porta and portb must not exceed 100ma. the sum of all i oh for portc must not exceed 200ma. the sum of all i oh for portd and pins pe[0-1] on porte must not exceed 200ma. the sum of all i oh for pe[2-3] on porte, portr and pdi must not exceed 100ma. 2. the sum of all i ol for porta and portb must not exceed 100ma. the sum of all i ol for portc must not not exceed 200ma. the sum of all i ol for portd and pins pe[0-1] on porte must not exceed 200ma. the sum of all i ol for pe[2-3] on porte, portr and pdi must not exceed 100ma . symbol parameter condition min. typ. max. units i oh (1) / i ol (2) i/o pin source/sink current -20 20 ma v ih high level input voltage v cc = 2.7- 3.6v 2.0 v cc +0.3 v v cc = 2.0 - 2.7v 0.7*v cc v cc +0.3 v cc = 1.6 - 2.0v 0.8*v cc v cc +0.3 v il low level input voltage v cc = 2.7- 3.6v -0.3 0.8 v v cc = 2.0 - 2.7v -0.3 0.3*v cc v cc = 1.6 - 2.0v -0.3 0.2*v cc v oh high level output voltage v cc = 3.0 - 3.6v i oh = -2ma 2.4 0.94*v cc v v cc = 2.3 - 2.7v i oh = -1ma 2.0 0.96*v cc i oh = -2ma 1.7 0.92*v cc v cc = 3.3v i oh = -8ma 2.6 2.9 v cc = 3.0v i oh = -6ma 2.1 2.6 v cc = 1.8v i oh = -2ma 1.4 1.6 v ol low level output voltage v cc = 3.0 - 3.6v i ol = 2ma 0.02*v cc 0.4 v v cc = 2.3 - 2.7v i ol = 1ma 0.01*v cc 0.4 i ol = 2ma 0.02*v cc 0.7 v cc = 3.3v i ol = 15ma 0.4 0.76 v cc = 3.0v i ol = 10ma 0.3 0.64 v cc = 1.8v i ol = 5ma 0.2 0.46 i in input leakage current t = 25c <0.01 0.1 a xosc and tosc pins <0.02 1.1 r p pull/buss keeper resistor 24 k ? t r rise time no load 4.0 ns slew rate limitation 7.0
120 xmega a4u [datasheet] 8387d?avr?02/2013 36.3.6 adc characteristics table 36-72. power supply, reference and input range. table 36-73. clock and timing. symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1.0 av cc - 0.6 v r in input resistance switched 4.0 k ? c sample input capacitance switched 4.4 pf r aref reference input resistance (leakage only) >10 m ? c aref reference input capacitance static load 7.0 pf v in input range -0.1 av cc + 0.1 v conversion range differential mode, vinp - vinn -v ref v ref v conversion range single ended unsigned mode, vinp - ? v v ref - ? v v ? v fixed offset voltage 190 lsb symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 2000 khz measuring internal signals 100 125 f adc sample rate current limitation (currlimit) off 100 2000 ksps currlimit = low 100 1500 currlimit = medium 100 1000 currlimit = high 100 500 sampling time 1/2 clk adc cycle 0.25 5 s conversion time (latency) (res+2)/2+(gain !=0) res (resolution) = 8 or 12 5 8 clk adc cycles start-up time adc clock cycles 12 24 clk adc cycles adc settling time after changing reference or input mode 7 7 clk adc cycles after adc flush 1 1
121 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-74. accuracy characteristics. notes: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 5% to 95% input voltage range . 2. unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external v ref is used. table 36-75. gain stage characteristics. symbol parameter condition (2) min. typ. max. units res resolution programmable to 8 or 12 bit 8 12 12 bits inl (1) integral non-linearity 500ksps v cc -1.0v < v ref < v cc -0.6v 1.2 2 lsb all v ref 1.5 3 2000ksps v cc -1.0v < v ref < v cc -0.6v 1.0 2 all v ref 1.5 3 dnl (1) differential non-linearity guaranteed monotonic <0.8 <1 lsb offset error -1 mv temperature drift <0.01 mv/k operating voltage drift <0.6 mv/v gain error differential mode external reference -1 mv av cc /1.6 10 av cc /2.0 8 bandgap 5 temperature drift <0.02 mv/k operating voltage drift <0.5 mv/v noise differential mode, shorted input 2msps, v cc = 3.6v, clk per = 16mhz 0.4 mv rms symbol parameter condition min. typ. max. units r in input resistance switched in normal mode 4.0 k ? c sample input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 v cc - 0.6 v propagation delay adc conversion rate 1.0 clk adc cycles sample rate same as adc 100 1000 khz inl (1) integral non-linearity 500ksps all gain settings 1.5 4.0 lsb gain error 1x gain, normal mode -0.8 % 8x gain, normal mode -2.5 64x gain, normal mode -3.5
122 xmega a4u [datasheet] 8387d?avr?02/2013 note: 1. maximum numbers are based on characterisation and not test ed in production, and valid for 5% to 95% input voltage range. 36.3.7 dac characteristics table 36-76. power supply, reference and output range. table 36-77. clock and timing. offset error, input referred 1x gain, normal mode -2 mv 8x gain, normal mode -5 64x gain, normal mode -4 noise 1x gain, normal mode v cc = 3.6v ext. v ref 0.5 mv rms 8x gain, normal mode 1.5 64x gain, normal mode 11 symbol parameter condition min. typ. max. units symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v av ref external reference voltage 1.0 v cc - 0.6 v r channel dc output impedance 50 ? linear output voltage range 0.15 av cc -0.15 v r aref reference input resistance >10 m ? caref reference input capacitance static load 7 pf minimum resistance load 1.0 k ? maximum capacitance load 100 pf 1000 ? serial resistance 1.0 nf output sink/source operating within accuracy specification av cc /1000 ma safe operation 10 symbol parameter condition min. typ. max. units f dac conversion rate c load =100pf, maximum step size normal mode 0 1000 ksps low power mode 500
123 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-78. accuracy characteristics. note: 1. maximum numbers are based on charac terisation and not tested in production, and valid for 5% to 95% output voltage range . symbol parameter condition min. typ. max. units res input resolution 12 bits inl (1) integral non-linearity v ref = ext 1.0v v cc = 1.6v 2.0 3.0 lsb v cc = 3.6v 1.5 2.5 v ref =av cc v cc = 1.6v 2.0 4.0 v cc = 3.6v 1.5 4.0 v ref =int1v v cc = 1.6v 5.0 v cc = 3.6v 5.0 dnl (1) differential non-linearity v ref =ext 1.0v v cc = 1.6v 1.5 3.0 lsb v cc = 3.6v 0.6 1.5 v ref =av cc v cc = 1.6v 1.0 3.5 v cc = 3.6v 0.6 1.5 v ref =int1v v cc = 1.6v 4.5 v cc = 3.6v 4.5 gain error after calibration <4.0 lsb gain calibration step size 4.0 lsb gain calibration drift v ref = ext 1.0v <0.2 mv/k offset error after calibration <1.0 lsb offset calibration step size 1.0
124 xmega a4u [datasheet] 8387d?avr?02/2013 36.3.8 analog comparator characteristics table 36-79. analog comparator characteristics. 36.3.9 bandgap and internal 1.0v reference characteristics table 36-80. bandgap and internal 1.0v reference characteristics. symbol parameter condition min. typ. max. units v off input offset voltage <10 mv i lk input leakage current <1 na input voltage range -0.1 av cc v ac startup time 100 s v hys1 hysteresis, none 0 mv v hys2 hysteresis, small mode = high speed (hs) 20 mv mode = low power (lp) 30 v hys3 hysteresis, large mode = hs 35 mv mode = lp 60 t delay propagation delay v cc = 3.0v, t= 85c mode = hs 30 90 ns mode = hs 30 v cc = 3.0v, t= 85c mode = lp 130 500 mode = lp 130 64-level voltage scaler integral non-linearity (inl) 0.3 0.5 lsb symbol parameter condition min. typ. max. units startup time as reference for adc or dac 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t= 85c, after calibration 0.99 1 1.01 v variation over voltage and temperature relative to t= 85c, v cc = 3.0v 1.5 %
125 xmega a4u [datasheet] 8387d?avr?02/2013 36.3.10 brownout detection characteristics table 36-81. brownout detection characteristics. 36.3.11 external reset characteristics table 36-82. external reset characteristics. 36.3.12 power-on reset characteristics table 36-83. power-on reset characteristics. note: 1. v pot- values are only valid when bod is disabled. when bod is enabled v pot- = v pot+ . symbol parameter condition min. typ. max. units v bot bod level 0 falling v cc 1.50 1.62 1.72 v bod level 1 falling v cc 1.8 bod level 2 falling v cc 2.0 bod level 3 falling v cc 2.2 bod level 4 falling v cc 2.4 bod level 5 falling v cc 2.6 bod level 6 falling v cc 2.8 bod level 7 falling v cc 3.0 t bod detection time continuous mode 0.4 s sampled mode 1000 v hyst hysteresis 1.2 % symbol parameter condition min. typ. max. units t ext minimum reset pulse width 1000 95 ns v rst reset threshold voltage (v ih ) v cc = 2.7 - 3.6v 0.60v cc v v cc = 1.6 - 2.7v 0.60v cc reset threshold voltage (v il ) v cc = 2.7 - 3.6v 0.50v cc v cc = 1.6 - 2.7v 0.40v cc r rst reset pin pull-up resistor 25 k ? symbol parameter condition min. typ. max. units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.0 v pot+ por threshold voltage rising v cc 1.3 1.59
126 xmega a4u [datasheet] 8387d?avr?02/2013 36.3.13 flash and eeprom memory characteristics table 36-84. endurance and data retention. table 36-85. progr amming time. notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. 36.3.14 clock and oscillator characteristics 36.3.14.1 calibrated 32.768khz internal oscillator characteristics table 36-86. 32.768khz internal oscillator characteristics. symbol parameter condition min. typ. max. units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 80k cycle 85c 30k data retention 25c 100 year 55c 25 symbol parameter condition min. typ. (1) max. units chip erase 64kb flash, eeprom (2) and sram erase 55 ms application erase section erase 6 ms flash page erase 4 ms page write 4 atomic page erase and write 8 eeprom page erase 4 ms page write 4 atomic page erase and write 8 symbol parameter condition min. typ. max. units frequency 32.768 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 %
127 xmega a4u [datasheet] 8387d?avr?02/2013 36.3.14.2calibrated 2mhz rc internal oscillator characteristics table 36-87. 2mhz internal oscillator characteristics. 36.3.14.3 calibrated and tunable 32mhz internal oscillator characteristics table 36-88. 32mhz internal oscillator characteristics. 36.3.14.4 32khz internal ulp oscillator characteristics table 36-89. 32khz internal ulp oscillator characteristics. symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.2 mhz factory calibrated frequency 2.0 mhz factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 % dfll calibration stepsize 0.21 % symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 30 55 mhz factory calibrated frequency 32 mhz factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 % dfll calibration step size 0.22 % symbol parameter condition min. typ. max. units factory calibrated frequency 32 khz factory calibrated accuracy t = 85c, v cc = 3.0v -12 12 % accuracy -30 30 %
128 xmega a4u [datasheet] 8387d?avr?02/2013 36.3.14.5internal phase locked l oop (pll) characteristics table 36-90. internal pll characteristics. note: 1. the maximum output frequency vs. supply voltage is linear be tween 1.8v and 2.7v, and can never be higher than four times the maximum cpu frequency. 36.3.14.6external clock characteristics figure 36-17.external clock drive waveform table 36-91. external clock used as system clock without prescaling. note: 1. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. symbo l parameter condition min. typ. max. units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.6 - 1.8v 20 48 mhz v cc = 2.7 - 3.6v 20 128 start-up time 25 s re-lock time 25 s t ch t cl t ck t ch v il1 v ih1 t cr t cf symbol parameter condition min. typ. max. units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 ? t ck change in period from one clock cycle to the next 10 %
129 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-92. external clock with prescaler (1) for system clock. notes: 1. system clock prescale rs must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. 36.3.14.7external 16mhz crystal o scillator and xosc characteristic table 36-93. external 16mhz crystal oscillator and xosc characteristics. symbol parameter condition min. typ. max. units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 ? t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units cycle to cycle jitter xoscpwr=0 frqrange=0 <10 ns frqrange=1, 2, or 3 <1 xoscpwr=1 <1 long term jitter xoscpwr=0 frqrange=0 <6 ns frqrange=1, 2, or 3 <0.5 xoscpwr=1 <0.5 frequency error xoscpwr=0 frqrange=0 <0.1 % frqrange=1 <0.05 frqrange=2 or 3 <0.005 xoscpwr=1 <0.005
130 xmega a4u [datasheet] 8387d?avr?02/2013 duty cycle xoscpwr=0 frqrange=0 40 % frqrange=1 42 frqrange=2 or 3 45 xoscpwr=1 48 r q negative impedance (1) xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 2.4k ? 1mhz crystal, cl=20pf 8.7k 2mhz crystal, cl=20pf 2.1k xoscpwr=0, frqrange=1, cl=20pf 2mhz crystal 4.2k 8mhz crystal 250 9mhz crystal 195 xoscpwr=0, frqrange=2, cl=20pf 8mhz crystal 360 9mhz crystal 285 12mhz crystal 155 xoscpwr=0, frqrange=3, cl=20pf 9mhz crystal 365 12mhz crystal 200 16mhz crystal 105 xoscpwr=1, frqrange=0, cl=20pf 9mhz crystal 435 12mhz crystal 235 16mhz crystal 125 xoscpwr=1, frqrange=1, cl=20pf 9mhz crystal 495 12mhz crystal 270 16mhz crystal 145 xoscpwr=1, frqrange=2, cl=20pf 12mhz crystal 305 16mhz crystal 160 xoscpwr=1, frqrange=3, cl=20pf 12mhz crystal 380 16mhz crystal 205 esr sf = safety factor min(r q )/sf k ? c xtal1 parasitic capacitance xtal1 pin 5.60 pf c xtal2 parasitic capacitance xtal2 pin 7.62 pf c load parasitic capacitance load 3.23 pf symbol parameter condition min. typ. max. units
131 xmega a4u [datasheet] 8387d?avr?02/2013 note: 1. numbers for negative impedance are not tested in production but guaranteed from design and characterization 36.3.14.8external 32.768khz crystal o scillator and tosc characteristics table 36-94. external 32.768khz crystal o scillator and tosc characteristics. note: 1. see figure 36-18 for definition. figure 36-18.tosc input capacitance. the parasitic capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. symbol parameter condition min. typ. max. units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k ? crystal load capacitance 9.0pf 35 c tosc1 parasitic capacitance tosc1 pin 5.4 pf alternate tosc location 4.0 c tosc2 parasitic capacitance tosc2 pin 7.1 pf alternate tosc location 4.0 recommended safety factor capacitance load matched to crystal specification 3 c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal
132 xmega a4u [datasheet] 8387d?avr?02/2013 36.3.15 spi characteristics figure 36-19.spi timing requirements in master mode. figure 36-20.spi timing requirements in slave mode. msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
133 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-95. spi timing characteristics and requirements. symbol parameter condition min. typ. max. units t sck sck period master (see table 21-4 in xmega au manual) ns t sckw sck high/low width master 0.5sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 11 t mih miso hold after sck master 0 t mos mosi setup sck master 0.5sck t moh mosi hold after sck master 1.0 t ssck slave sck period slave 4t clk per t ssckw sck high/low width slave 2t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3.0 t sih mosi hold after sck slave t per t sss ss setup to sck slave 20 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8.0 t soh miso hold after sck slave 13.0 t soss miso setup after ss low slave 11.0 t sosh miso hold after ss high slave 8.0
134 xmega a4u [datasheet] 8387d?avr?02/2013 36.3.16 two-wire interf ace characteristics table 36-96 describes the requirements for devices connected to the two-wire interface bus. the atmel avr xmega two-wire interface meets or exceeds these require ments under the noted conditions. timing symbols refer to figure 36- 21 . figure 36-21.two-wire interface bus timing. table 36-96. two-wire interface characteristics. t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto symbol parameter condition min. typ. max. units v ih input high voltage 0.7v cc v cc +0.5 v v il input low voltage -0.5 0.3v cc v v hys hysteresis of schmitt trigger inputs 0.05v cc (1) 0 v v ol output low voltage 3ma, sink current 0 0.4 v t r rise time for both sda and scl 20+0.1c b (1)(2) 0 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20+0.1c b (1)(2) 300 ns t sp spikes suppressed by input filter 0 50 ns i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 0 10 pf f scl scl clock frequency f per (3) >max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl ? 100khz ? f scl > 100khz t hd;sta hold time (repeated) start condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl ? 100khz 4.7 s f scl > 100khz 1.3 t high high period of scl clock f scl ? 100khz 4.0 s f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl ? 100khz 4.7 s f scl > 100khz 0.6 v cc 0.4 v ? 3 ma --------------------------- - 100 ns c b -------------- - 300 ns c b -------------- -
135 xmega a4u [datasheet] 8387d?avr?02/2013 notes: 1. required only for f scl > 100khz. 2. c b = capacitance of one bus line in pf. 3. f per = peripheral clock frequency. t hd;dat data hold time f scl ? 100khz 0 3.45 s f scl > 100khz 0 0.9 t su;dat data setup time f scl ? 100khz 250 s f scl > 100khz 100 t su;sto setup time for stop condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl ? 100khz 4.7 s f scl > 100khz 1.3 symbol parameter condition min. typ. max. units
136 xmega a4u [datasheet] 8387d?avr?02/2013 36.4 atxmega128a4u 36.4.1 absolute maximum ratings stresses beyond those listed in table 36-97 may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. table 36-97. absolute maximum ratings. 36.4.2 general operating ratings the device must operate within the ratings listed in table 36-98 in order for all other electrical characteristics and typical characteristics of the device to be valid. table 36-98. general operating conditions. table 36-99. operating voltage and frequency. symbol parameter condition min. typ. max. units v cc power supply voltage -0.3 4 v i vcc current into a v cc pin 200 ma i gnd current out of a gnd pin 200 ma v pin pin voltage with respect to gnd and v cc -0.5 v cc +0.5 v i pin i/o pin sink/source current -25 25 ma t a storage temperature -65 150 c t j junction temperature 150 c symbol parameter condition min. typ. max. units v cc power supply voltage 1.60 3.6 v av cc analog supply voltage 1.60 3.6 v t a temperature range -40 85 c t j junction temperature -40 105 c symbol parameter condition min. typ. max. units clk cpu cpu clock frequency v cc = 1.6v 0 12 mhz v cc = 1.8v 0 12 v cc = 2.7v 0 32 v cc = 3.6v 0 32
137 xmega a4u [datasheet] 8387d?avr?02/2013 the maximum cpu clock frequency depends on v cc . as shown in figure 36-22 the frequency vs. v cc curve is linear between 1.8v < v cc <2.7v. figure 36-22.maximu m frequency vs. v cc . 1.8 12 32 mhz v 2.7 3.6 1.6 safe operating area
138 xmega a4u [datasheet] 8387d?avr?02/2013 36.4.3 current consumption table 36-100.current consumption for active mode and sleep modes. notes: 1. all power reduction registers set. 2. maximum limits are based on characterization, and not tested in production. symbol parameter condition min. typ. max. units i cc active power consumption (1) 32khz, ext. clk v cc = 1.8v 55 a v cc = 3.0v 135 1mhz, ext. clk v cc = 1.8v 255 v cc = 3.0v 535 2mhz, ext. clk v cc = 1.8v 460 600 v cc = 3.0v 1.0 1.4 ma 32mhz, ext. clk 9.5 12 idle power consumption (1) 32khz, ext. clk v cc = 1.8v 2.9 a v cc = 3.0v 3.9 1mhz, ext. clk v cc = 1.8v 62 v cc = 3.0v 118 2mhz, ext. clk v cc = 1.8v 125 225 v cc = 3.0v 240 350 32mhz, ext. clk 3.8 5.5 ma power-down power consumption t=25c v cc = 3.0v 0.1 1.0 a t=85c 1.5 4.5 wdt and sampled bod enabled, t=25c v cc = 3.0v 1.4 3.0 wdt and sampled bod enabled, t = 85c 2.8 6.0 power-save power consumption (2) rtc from ulp clock, wdt and sampled bod enabled, t = 25c v cc = 1.8v 1.2 a v cc = 3.0v 1.5 rtc from 1.024khz low power 32.768khz tosc, t = 25c v cc = 1.8v 0.6 2.0 v cc = 3.0v 0.7 2.0 rtc from low power 32.768khz tosc, t = 25c v cc = 1.8v 0.8 3.0 v cc = 3.0v 1.0 3.0 reset power consumption current through reset pin substracted v cc = 3.0v 300 a
139 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-101.current consumption for modules and peripherals. note: 1. all parameters measured as the difference in current consumption between module enabled and disabled. all data at v cc = 3.0v, clk sys = 1mhz external clock without prescaling, t = 25c unless other conditions are given. symbol parameter condition (1) min. typ. max. units i cc ulp oscillator 1.0 a 32.768khz int. oscillator 29 a 2mhz int. oscillator 85 a dfll enabled with 32.768khz int. osc. as reference 115 32mhz int. oscillator 270 a dfll enabled with 32.768khz int. osc. as reference 440 pll 20x multiplication factor, 32mhz int. osc. div4 as reference 320 a watchdog timer 1.0 a bod continuous mode 138 a sampled mode, includes ulp oscillator 1.2 internal 1.0v reference 260 a temperature sensor 250 a adc 250ksps v ref = ext ref 3.0 ma currlimit = low 2.6 currlimit = medium 2.1 currlimit = high 1.6 dac 250ksps v ref = ext ref no load normal mode 1.9 ma low power mode 1.1 ac high speed mode 330 a low power mode 130 dma 615kbps between i/o registers and sram 108 a timer/counter 16 a usart rx and tx enabled, 9600 baud 2.5 a flash memory and eeprom programming 4.0 8.0 ma
140 xmega a4u [datasheet] 8387d?avr?02/2013 36.4.4 wake-up time from sleep modes table 36-102. device wake-up ti me from sleep modes with various system clock sources. note: 1. the wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see figure 36-23 . all peripherals and modules start execution from the first clock cycle, ex pect the cpu that is halted for four cloc k cycles before program execution starts. figure 36-23.wake-up time definition. symbol parameter condition min. typ. (1) max. units t wakeup wake-up time from idle, standby, and extended standby mode external 2mhz clock 2.0 s 32.768khz internal oscillator 120 2mhz internal oscillator 2.0 32mhz internal oscillator 0.2 wake-up time from power-save and power-down mode external 2mhz clock 4.5 s 32.768khz internal oscillator 320 2mhz internal oscillator 9.0 32mhz internal oscillator 5.0 wakeup request clock output wakeup time
141 xmega a4u [datasheet] 8387d?avr?02/2013 36.4.5 i/o pin characteristics the i/o pins comply with the jedec lv ttl and lvcmos specification and the high- and low level input and output voltage limits reflect or exceed this specification. table 36-103.i/o pin characteristics. notes: 1. the sum of all i oh for porta and portb must not exceed 100ma. the sum of all i oh for portc must not exceed 200ma. the sum of all i oh for portd and pins pe[0-1] on porte must not exceed 200ma. the sum of all i oh for pe[2-3] on porte, portr and pdi must not exceed 100ma. 2. the sum of all i ol for porta and portb must not exceed 100ma. the sum of all i ol for portc must not not exceed 200ma. the sum of all i ol for portd and pins pe[0-1] on porte must not exceed 200ma. the sum of all i ol for pe[2-3] on porte, portr and pdi must not exceed 100ma. symbol parameter condition min. typ. max. units i oh (1) / i ol (2) i/o pin source/sink current -20 20 ma v ih high level input voltage v cc = 2.7 - 3.6v 2.0 v cc +0.3 v v cc = 2.0 - 2.7v 0.7*v cc v cc +0.3 v cc = 1.6 - 2.0v 0.8*v cc v cc +0.3 v il low level input voltage v cc = 2.7- 3.6v -0.3 0.8 v v cc = 2.0 - 2.7v -0.3 0.3*v cc v cc = 1.6 - 2.0v -0.3 0.2*v cc v oh high level output voltage v cc = 3.0 - 3.6v i oh = -2ma 2.4 0.94*v cc v v cc = 2.3 - 2.7v i oh = -1ma 2.0 0.96*v cc i oh = -2ma 1.7 0.92*v cc v cc = 3.3v i oh = -8ma 2.6 2.9 v cc = 3.0v i oh = -6ma 2.1 2.6 v cc = 1.8v i oh = -2ma 1.4 1.6 v ol low level output voltage v cc = 3.0 - 3.6v i ol = 2ma 0.05 0.4 v v cc = 2.3 - 2.7v i ol = 1ma 0.03 0.4 i ol = 2ma 0.06 0.7 v cc = 3.3v i ol = 15ma 0.4 0.76 v cc = 3.0v i ol = 10ma 0.3 0.64 v cc = 1.8v i ol = 5ma 0.2 0.46 i in input leakage current t = 25c <0.01 0.1 a r p pull/buss keeper resistor 24 k ? t r rise time no load 4.0 ns slew rate limitation 7.0
142 xmega a4u [datasheet] 8387d?avr?02/2013 36.4.6 adc characteristics table 36-104.power supply, reference and input range. table 36-105.cloc k and timing. symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1 av cc - 0.6 v r in input resistance switched 4.0 k ? c sample input capacitance switched 4.4 pf r aref reference input resistance (leakage only) >10 m ? c aref reference input capacitance static load 7 pf v in input range -0.1 av cc + 0.1 v conversion range differential mode, vinp - vinn -v ref v ref v conversion range single ended unsigned mode, vinp - ? v v ref - ? v v ? v fixed offset voltage 190 lsb symbol parameter condition min. typ. max. units clk adc adc clock frequency maximum is 1/4 of peripheral clock frequency 100 2000 khz measuring internal signals 100 125 f adc sample rate current limitation (currlimit) off 100 2000 ksps currlimit = low 100 1500 currlimit = medium 100 1000 currlimit = high 100 500 sampling time 1/2 clk adc cycle 0.25 5 s conversion time (latency) (res+2)/2+(gain !=0) res (resolution) = 8 or 12 5 8 clk adc cycles start-up time adc clock cycles 12 24 clk adc cycles adc settling time after changing reference or input mode 7 7 clk adc cycles after adc flush 1 1
143 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-106.accura cy characteristics. notes: 1. maximum numbers are based on characterisation and not te sted in production, and valid for 5% to 95% input voltage range . 2. unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external v ref is used. table 36-107.gain st age characteristics. symbol parameter condition (2) min. typ. max. units res resolution programmable to 8 or 12 bit 8 12 12 bits inl (1) integral non-linearity 500ksps v cc -1.0v < v ref < v cc -0.6v 1.2 2 lsb all v ref 1.5 3 2000ksps v cc -1.0v < v ref < v cc -0.6v 1.0 2 all v ref 1.5 3 dnl (1) differential non-linearity guaranteed monotonic <0.8 <1 lsb offset error -1.0 mv temperature drift <0.01 mv/k operating voltage drift <0.6 mv/v gain error differential mode external reference -1 mv av cc /1.6 10 av cc /2.0 8.0 bandgap 5 temperature drift <0.02 mv/k operating voltage drift <0.5 mv/v noise differential mode, shorted input 2msps, v cc = 3.6v, clk per = 16mhz 0.4 mv rms symbol parameter condition min. typ. max. units r in input resistance switched in normal mode 4.0 k ? c sample input capacitance switched in normal mode 4.4 pf signal range gain stage output 0 v cc - 0.6 v propagation delay adc conversion rate 1.0 clk adc cycles sample rate same as adc 100 1000 khz inl (1) integral non-linearity 500ksps all gain settings 1.5 4.0 lsb gain error 1x gain, normal mode -0.8 % 8x gain, normal mode -2.5 64x gain, normal mode -3.5
144 xmega a4u [datasheet] 8387d?avr?02/2013 note: 1. maximum numbers are based on characterisation and not test ed in production, and valid for 5% to 95% input voltage range. 36.4.7 dac characteristics table 36-108.power supply, reference and output range. table 36-109.cloc k and timing. offset error, input referred 1x gain, normal mode -2.0 mv 8x gain, normal mode -5.0 64x gain, normal mode -4.0 noise 1x gain, normal mode v cc = 3.6v ext. v ref 0.5 mv rms 8x gain, normal mode 1.5 64x gain, normal mode 11 symbol parameter condition min. typ. max. units symbol parameter condition min. typ. max. units av cc analog supply voltage v cc - 0.3 v cc + 0.3 av ref external reference voltage 1.0 v cc - 0.6 v r channel dc output impedance 50 ? linear output voltage range 0.15 av cc -0.15 v r aref reference input resistance >10 m ? caref reference input capacitance static load 7.0 pf minimum resistance load 1 k ? maximum capacitance load 100 pf 1000 ? serial resistance 1 nf output sink/source operating within accuracy specification av cc /1000 ma safe operation 10 symbol parameter condition min. typ. max. units f dac conversion rate c load =100pf, maximum step size normal mode 0 1000 ksps low power mode 500
145 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-110.accuracy characteristics. note: 1. maximum numbers are based on charac terisation and not tested in production, and valid for 5% to 95% output voltage range . symbol parameter condition min. typ. max. units res input resolution 12 bits inl (1) integral non-linearity v ref = ext 1.0v v cc = 1.6v 2.0 3.0 lsb v cc = 3.6v 1.5 2.5 v ref =av cc v cc = 1.6v 2.0 4.0 v cc = 3.6v 1.5 4.0 v ref =int1v v cc = 1.6v 5.0 v cc = 3.6v 5.0 dnl (1) differential non-linearity v ref =ext 1.0v v cc = 1.6v 1.5 3.0 lsb v cc = 3.6v 0.6 1.5 v ref =av cc v cc = 1.6v 1.0 3.5 v cc = 3.6v 0.6 1.5 v ref =int1v v cc = 1.6v 4.5 v cc = 3.6v 4.5 gain error after calibration <4.0 lsb gain calibration step size 4.0 lsb gain calibration drift v ref = ext 1.0v <0.2 mv/k offset error after calibration <1.0 lsb offset calibration step size 1.0
146 xmega a4u [datasheet] 8387d?avr?02/2013 36.4.8 analog comparator characteristics table 36-111. analog comparator characteristics. 36.4.9 bandgap and internal 1.0v reference characteristics table 36-112. bandgap and internal 1.0v reference characteristics. symbol parameter condition min. typ. max. units v off input offset voltage <10 mv i lk input leakage current <1 na input voltage range -0.1 av cc v ac startup time 100 s v hys1 hysteresis, none 0 mv v hys2 hysteresis, small mode = high speed (hs) 13 mv mode = low power (lp) 30 v hys3 hysteresis, large mode = hs 30 mv mode = lp 60 t delay propagation delay v cc = 3.0v, t= 85c mode = hs 30 90 ns mode = hs 30 v cc = 3.0v, t= 85c mode = lp 130 500 mode = lp 130 64-level voltage scaler integral non-linearity (inl) 0.3 0.5 lsb symbol parameter condition min. typ. max. units startup time as reference for adc or dac 1 clk per + 2.5s s as input voltage to adc and ac 1.5 bandgap voltage 1.1 v int1v internal 1.00v reference t= 85c, after calibration 0.99 1.0 1.01 v variation over voltage and temperature relative to t= 85c, v cc = 3.0v 1.5 %
147 xmega a4u [datasheet] 8387d?avr?02/2013 36.4.10 brownout detection characteristics table 36-113.brownout de tection characteristics. 36.4.11 external reset characteristics table 36-114.external reset characteristics. 36.4.12 power-on reset characteristics table 36-115. power-on reset characteristics. note: 1. v pot- values are only valid when bod is disabled. when bod is enabled v pot- = v pot+ . symbol parameter condition min. typ. max. units v bot bod level 0 falling v cc 1.50 1.62 1.72 v bod level 1 falling v cc 1.8 bod level 2 falling v cc 2.0 bod level 3 falling v cc 2.2 bod level 4 falling v cc 2.4 bod level 5 falling v cc 2.6 bod level 6 falling v cc 2.8 bod level 7 falling v cc 3.0 t bod detection time continuous mode 0.4 s sampled mode 1000 v hyst hysteresis 1.2 % symbol parameter condition min. typ. max. units t ext minimum reset pulse width 1000 95 ns v rst reset threshold voltage (v ih ) v cc = 2.7 - 3.6v 0.60v cc v v cc = 1.6 - 2.7v 0.60v cc reset threshold voltage (v il ) v cc = 2.7 - 3.6v 0.50v cc v cc = 1.6 - 2.7v 0.40v cc r rst reset pin pull-up resistor 25 k ? symbol parameter condition min. typ. max. units v pot- (1) por threshold voltage falling v cc v cc falls faster than 1v/ms 0.4 1.0 v v cc falls at 1v/ms or slower 0.8 1.0 v pot+ por threshold voltage rising v cc 1.3 1.59 mv
148 xmega a4u [datasheet] 8387d?avr?02/2013 36.4.13 flash and eeprom memory characteristics table 36-116.endurance and data retention. table 36-117.programming time. notes: 1. programming is timed from the 2mhz internal oscillator. 2. eeprom is not erased if the eesave fuse is programmed. 36.4.14 clock and oscillator characteristics 36.4.14.1calibrated 32.768khz internal oscillator characteristics table 36-118.32.768khz internal oscillator characteristics. symbol parameter condition min. typ. max. units flash write/erase cycles 25c 10k cycle 85c 10k data retention 25c 100 year 55c 25 eeprom write/erase cycles 25c 80k cycle 85c 30k data retention 25c 100 year 55c 25 symbol parameter condition min. typ. (1) max. units chip erase 128kb flash, eeprom (2) and sram erase 75 ms application erase section erase 6 ms flash page erase 4 ms page write 4 atomic page erase and write 8 eeprom page erase 4 ms page write 4 atomic page erase and write 8 symbol parameter condition min. typ. max. units frequency 32.768 khz factory calibration accuracy t = 85 ? c, v cc = 3.0v -0.5 0.5 % user calibration accuracy -0.5 0.5 %
149 xmega a4u [datasheet] 8387d?avr?02/2013 36.4.14.2calibrated 2mhz rc internal oscillator characteristics table 36-119.2mhz internal oscillator characteristics. 36.4.14.3calibrated and tunable 32mhz in ternal oscillator characteristics table 36-120.32mhz internal oscillator characteristics. 36.4.14.432khz internal ulp oscillator characteristics table 36-121.32khz internal ulp oscillator characteristics. symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 1.8 2.2 mhz factory calibrated frequency 2.0 mhz factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 % dfll calibration stepsize 0.21 % symbol parameter condition min. typ. max. units frequency range dfll can tune to this frequency over voltage and temperature 30 55 mhz factory calibrated frequency 32 mhz factory calibration accuracy t = 85 ? c, v cc = 3.0v -1.5 1.5 % user calibration accuracy -0.2 0.2 % dfll calibration step size 0.22 % symbol parameter condition min. typ. max. units output frequency 32 khz accuracy -30 30 %
150 xmega a4u [datasheet] 8387d?avr?02/2013 36.4.14.5internal phase locked l oop (pll) characteristics table 36-122.internal pll characteristics. note: 1. the maximum output frequency vs. supply voltage is linear be tween 1.8v and 2.7v, and can never be higher than four times the maximum cpu frequency. 36.4.14.6external clock characteristics figure 36-24.external clock drive waveform table 36-123.external clock used as system clock without prescaling. note: 1. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. symbo l parameter condition min. typ. max. units f in input frequency output frequency must be within f out 0.4 64 mhz f out output frequency (1) v cc = 1.6 - 1.8v 20 48 mhz v cc = 2.7 - 3.6v 20 128 start-up time 25 s re-lock time 25 s t ch t cl t ck t ch v il1 v ih1 t cr t cf symbol parameter condition min. typ. max. units 1/t ck clock frequency (1) v cc = 1.6 - 1.8v 0 12 mhz v cc = 2.7 - 3.6v 0 32 t ck clock period v cc = 1.6 - 1.8v 83.3 ns v cc = 2.7 - 3.6v 31.5 t ch clock high time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cl clock low time v cc = 1.6 - 1.8v 30.0 ns v cc = 2.7 - 3.6v 12.5 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 10 ns v cc = 2.7 - 3.6v 3 ? t ck change in period from one clock cycle to the next 10 %
151 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-124.external clock with prescaler (1) for system clock. notes: 1. system clock prescale rs must be set so that maximum cpu clock frequency for device is not exceeded. 2. the maximum frequency vs. supply voltage is linear between 1.6v and 2.7v, and the same applies for all other parameters with supply voltage conditions. 36.4.14.7external 16mhz crystal o scillator and xosc characteristic table 36-125.external 16mhz crystal o scillator and xosc characteristics. symbol parameter condition min. typ. max. units 1/t ck clock frequency (2) v cc = 1.6 - 1.8v 0 90 mhz v cc = 2.7 - 3.6v 0 142 t ck clock period v cc = 1.6 - 1.8v 11 ns v cc = 2.7 - 3.6v 7 t ch clock high time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cl clock low time v cc = 1.6 - 1.8v 4.5 ns v cc = 2.7 - 3.6v 2.4 t cr rise time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 t cf fall time (for maximum frequency) v cc = 1.6 - 1.8v 1.5 ns v cc = 2.7 - 3.6v 1.0 ? t ck change in period from one clock cycle to the next 10 % symbol parameter condition min. typ. max. units cycle to cycle jitter xoscpwr=0 frqrange=0 <10 ns frqrange=1, 2, or 3 <1 xoscpwr=1 <1 long term jitter xoscpwr=0 frqrange=0 <6 ns frqrange=1, 2, or 3 <0.5 xoscpwr=1 <0.5 frequency error xoscpwr=0 frqrange=0 <0.1 % frqrange=1 <0.05 frqrange=2 or 3 <0.005 xoscpwr=1 <0.005
152 xmega a4u [datasheet] 8387d?avr?02/2013 duty cycle xoscpwr=0 frqrange=0 40 % frqrange=1 42 frqrange=2 or 3 45 xoscpwr=1 48 r q negative impedance (1) xoscpwr=0, frqrange=0 0.4mhz resonator, cl=100pf 2.4k ? 1mhz crystal, cl=20pf 8.7k 2mhz crystal, cl=20pf 2.1k xoscpwr=0, frqrange=1, cl=20pf 2mhz crystal 4.2k 8mhz crystal 250 9mhz crystal 195 xoscpwr=0, frqrange=2, cl=20pf 8mhz crystal 360 9mhz crystal 285 12mhz crystal 155 xoscpwr=0, frqrange=3, cl=20pf 9mhz crystal 365 12mhz crystal 200 16mhz crystal 105 xoscpwr=1, frqrange=0, cl=20pf 9mhz crystal 435 12mhz crystal 235 16mhz crystal 125 xoscpwr=1, frqrange=1, cl=20pf 9mhz crystal 495 12mhz crystal 270 16mhz crystal 145 xoscpwr=1, frqrange=2, cl=20pf 12mhz crystal 305 16mhz crystal 160 xoscpwr=1, frqrange=3, cl=20pf 12mhz crystal 380 16mhz crystal 205 esr sf = safety factor min(rq)/sf k ? c xtal1 parasitic capacitance xtal1 pin 5.45 pf c xtal2 parasitic capacitance xtal2 pin 7.51 pf c load parasitic capacitance load 3.16 pf symbol parameter condition min. typ. max. units
153 xmega a4u [datasheet] 8387d?avr?02/2013 note: 1. numbers for negative impedance are not tested in production but guaranteed from design and characterization. 36.4.14.8external 32.768khz crystal o scillator and tosc characteristics table 36-126.external 32.768khz crystal oscillator and tosc characteristics. note: 1. see figure 36-25 for definition. figure 36-25.tosc input capacitance. the parasitic capacitance between the tosc pins is c l1 + c l2 in series as seen from the crystal when oscillating without external capacitors. symbol parameter condition min. typ. max. units esr/r1 recommended crystal equivalent series resistance (esr) crystal load capacitance 6.5pf 60 k ? crystal load capacitance 9.0pf 35 c tosc1 parasitic capacitance tosc1 pin 5.4 pf alternate tosc location 4.0 c tosc2 parasitic capacitance tosc2 pin 7.1 pf alternate tosc location 4.0 recommended safety factor capacitance load matched to crystal specification 3 c l1 c l2 2 c s o t 1 c s o t device internal external 32.768khz crystal
154 xmega a4u [datasheet] 8387d?avr?02/2013 36.4.15 spi characteristics figure 36-26.spi timing requirements in master mode. figure 36-27.spi timing requirements in slave mode. msb lsb msb lsb t mos t mis t mih t sckw t sck t moh t moh t sckf t sckr t sckw mo si (data output) mi so (data input) sck (cpol = 1) sck (cpol = 0) ss msb lsb msb lsb t sis t sih t ssckw t ssckw t ssck t ssh t sossh t sckr t sckf t sos t sss t sosss mi so (data output) mo si (data input) sck (cpol = 1) sck (cpol = 0) ss
155 xmega a4u [datasheet] 8387d?avr?02/2013 table 36-127.spi timing char acteristics and requirements. symbol parameter condition min. typ. max. units t sck sck period master (see table 21-4 in xmega au manual) ns t sckw sck high/low width master 0.5sck t sckr sck rise time master 2.7 t sckf sck fall time master 2.7 t mis miso setup to sck master 10 t mih miso hold after sck master 10 t mos mosi setup sck master 0.5sck t moh mosi hold after sck master 1 t ssck slave sck period slave 4t clk per t ssckw sck high/low width slave 2t clk per t ssckr sck rise time slave 1600 t ssckf sck fall time slave 1600 t sis mosi setup to sck slave 3 t sih mosi hold after sck slave tclk per t sss ss setup to sck slave 21 t ssh ss hold after sck slave 20 t sos miso setup sck slave 8 t soh miso hold after sck slave 13 t soss miso setup after ss low slave 11 t sosh miso hold after ss high slave 8
156 xmega a4u [datasheet] 8387d?avr?02/2013 36.4.16 two-wire interf ace characteristics table 36-128 describes the requirements for devices connected to the two-wire interface bus. the atmel avr xmega two-wire interface meets or exceeds these require ments under the noted conditions. timing symbols refer to figure 36- 28 . figure 36-28.two-wire interface bus timing. table 36-128.two-wire in terface characteristics. t hd;sta t of sda scl t low t high t su;sta t buf t r t hd;dat t su;dat t su;sto symbol parameter condition min. typ. max. units v ih input high voltage 0.7v cc v cc +0.5 v v il input low voltage 0.5 0.3v cc v v hys hysteresis of schmitt trigger inputs 0.05v cc (1) v v ol output low voltage 3ma, sink current 0 0.4 v t r rise time for both sda and scl 20+0.1c b (1)(2) 300 ns t of output fall time from v ihmin to v ilmax 10pf < c b < 400pf (2) 20+0.1c b (1)(2) 250 ns t sp spikes suppressed by input filter 0 50 ns i i input current for each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i capacitance for each i/o pin 10 pf f scl scl clock frequency f per (3) >max(10f scl , 250khz) 0 400 khz r p value of pull-up resistor f scl ? 100khz ? f scl > 100khz t hd;sta hold time (repeated) start condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t low low period of scl clock f scl ? 100khz 4.7 s f scl > 100khz 1.3 t high high period of scl clock f scl ? 100khz 4.0 s f scl > 100khz 0.6 t su;sta set-up time for a repeated start condition f scl ? 100khz 4.7 s f scl > 100khz 0.6 v cc 0.4 v ? 3 ma --------------------------- - 100 ns c b -------------- - 300 ns c b -------------- -
157 xmega a4u [datasheet] 8387d?avr?02/2013 notes: 1. required only for f scl > 100khz. 2. c b = capacitance of one bus line in pf. 3. f per = peripheral clock frequency. t hd;dat data hold time f scl ? 100khz 0 3.45 s f scl > 100khz 0 0.9 t su;dat data setup time f scl ? 100khz 250 s f scl > 100khz 100 t su;sto setup time for stop condition f scl ? 100khz 4.0 s f scl > 100khz 0.6 t buf bus free time between a stop and start condition f scl ? 100khz 4.7 s f scl > 100khz 1.3 symbol parameter condition min. typ. max. units
158 xmega a4u [datasheet] 8387d?avr?02/2013 37. typical characteristics 37.1 atxmega16a4u 37.1.1 current consumption 37.1.1.1 active mode supply current figure 37-1. active supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 37-2. active supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . 3.3v 3.0v 2.7v 2.2v 1.8v 0 60 120 180 240 300 360 420 480 540 600 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency [mhz] i cc [ a] 3.3v 3.0v 2.7v 0 2 4 6 8 10 12 0 4 8 121620242832 frequency [mhz] i cc [ma] 2.2v 1.8v
159 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-3. active mode supply current vs. v cc . f sys = 32.768khz internal oscillator . figure 37-4. active mode supply current vs. v cc . f sys = 1mhz external clock . 85c 25c -40c 40 50 60 70 80 90 100 110 120 130 140 150 160 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ a] 85c 25c -40c 100 160 220 280 340 400 460 520 580 640 700 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ a]
160 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-5. active mode supply current vs. v cc . f sys = 2mhz internal oscillator . figure 37-6. active mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz. 85c 25c -40c 400 500 600 700 800 900 1000 1100 1200 1300 1400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ a] 85c 25c -40c 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ma]
161 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-7. active mode supply current vs. v cc . f sys = 32mhz internal oscillator. 37.1.1.2 idle mode supply current figure 37-8. idle mode supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . 85c 25c -40c 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] i cc [ma] 3.3v 3.0v 2.7v 2.2v 1.8v 0 20 40 60 80 100 120 140 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency [mhz] i cc [a]
162 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-9. idle mode supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . figure 37-10. idle mode supply current vs. v cc . f sys = 32.768khz internal oscillator . 3.3v 3.0v 2.7v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 048121620242832 frequency [mhz] i cc [ma] 2.2v 1.8v 85c 25c -40c 27.0 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 32.5 33.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
163 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-11. idle mode supply current vs. v cc . f sys = 1mhz external clock . figure 37-12. idle mode supply current vs. v cc . f sys = 2mhz internal oscillator . 85c 25c -40c 50 60 70 80 90 100 110 120 130 140 150 160 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 160 180 200 220 240 260 280 300 320 340 360 380 400 420 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
164 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-13. idle mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz . figure 37-14. idle mode current vs. v cc . f sys = 32mhz internal oscillator . 85c 25c -40c 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ma] 85c 25c -40c 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] i cc [ma]
165 xmega a4u [datasheet] 8387d?avr?02/2013 37.1.1.3 power-down mode supply current figure 37-15. power-down mode supply current vs. temperature. all functions disabled . figure 37-16. power-down mode supply current vs. v cc . all functions disabled . 3.3v 3.0v 2.7v 2.2v 1.8v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 -40-30-20-10 0 102030405060708090 temperature [c] i cc [a] 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] i cc [a]
166 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-17. power-down mode supply current vs. v cc . watchdog and sampled bod enabled . 37.1.1.4 power-save mode supply current figure 37-18. power-save mode supply current vs.v cc . real time counter enabled and running from 1.024khz output of 32.768khz tosc. 85c 25c -40c 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] normal mode low-power mode 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
167 xmega a4u [datasheet] 8387d?avr?02/2013 37.1.1.5 standby mode supply current figure 37-19. standby supply current vs. v cc . standby, f sys =1mhz . figure 37-20. standby supply current vs. v cc . 25c, running from different crystal oscillators . 85c 25c -40c 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] i cc [a] 16mhz 12mhz 8mhz 2mhz 0.454mhz 160 200 240 280 320 360 400 440 480 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] i cc [a]
168 xmega a4u [datasheet] 8387d?avr?02/2013 37.1.2 i/o pin characteristics 37.1.2.1 pull-up figure 37-21. i/o pin pull-up resi stor current vs. input voltage. v cc = 1.8v . figure 37-22. i/o pin pull-up resi stor current vs. input voltage. v cc = 3.0v . 85 c 25 c -40 c 0 10 20 30 40 50 60 70 0.10.30.50.70.91.11.31.51.7 v pin [v] i [a] 85 c 25 c -40 c 0 15 30 45 60 75 90 105 120 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 v pin [v] i [ua]
169 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-23. i/o pin pull-up resi stor current vs. input voltage. v cc = 3.3v . 37.1.2.2 output voltage vs. sink/source current figure 37-24. i/o pin output voltage vs. source current. v cc = 1.8v . 85 c 25 c -40 c 0 15 30 45 60 75 90 105 120 135 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4 v pin [v] i [a] 85c 25c -40c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 i pin [ma] v pin [v] -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0
170 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-25. i/o pin output voltage vs. source current. v cc = 3.0v . figure 37-26. i/o pin output voltage vs. source current. v cc = 3.3v . 85c 25c -40c 0.5 1.0 1.5 2.0 2.5 3.0 -30 -25 -20 -15 -10 -5 0 i pin [ma] v pin [v] 85c 25c -40c 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -30 -25 -20 -15 -10 -5 0 i pin [ma] v pin [v]
171 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-27. i/o pin output voltage vs. source current. figure 37-28. i/o pin output voltage vs. sink current. v cc = 1.8v . 3.6v 3.3v 3.0v 2.7v 2.3v 1.8v 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -24 -21 -18 -15 -12 -9 -6 -3 0 i pin [ma] v pin [v] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 2 4 6 8 10 12 14 16 18 20 i pin [ma] v pin [v] 85c 25c -40c
172 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-29. i/o pin output voltage vs. sink current. v cc = 3.0v . figure 37-30. i/o pin output voltage vs. sink current. v cc = 3.3v . 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 3 6 9 12 15 18 21 24 27 30 i pin [ma] v pin [v] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 3 6 9 12151821242730 i pin [ma] v pin [v] -40c 25c 85c
173 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-31. i/o pin output voltage vs. sink current. 37.1.2.3 thresholds and hysteresis figure 37-32. i/o pin input threshold voltage vs. v cc. t = 25c . 0 0.3 0.6 0.9 1.2 1.5 0 5 10 15 20 25 30 i pin [ma] v pin [v] 1.8v 3.6v 3.3v 3.0v 2.7v 2.3v vil vih 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vthreshold [v]
174 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-33. i/o pin input threshold voltage vs. v cc . v ih i/o pin read as ?1? . figure 37-34. i/o pin input threshold voltage vs. v cc . v il i/o pin read as ?0? . 85c 25c -40c 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v threshold [v] 85c 25c -40c 0.57 0.72 0.87 1.02 1.17 1.32 1.47 1.62 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v threshold [v]
175 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-35. i/o pin input hysteresis vs. v cc . 37.1.3 adc characteristics figure 37-36. inl error vs. external v ref . t = 25 ? c, v cc = 3.6v, external reference . 85c 25c -40c 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.30 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v hysteresis [v] single-ended unsigned single-ended signed differential signed 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 v [v] inl [lsb] ref
176 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-37. inl error vs. sample rate. t = 25 ? c, v cc = 3.6v, v ref = 3.0v external . figure 37-38. inl error vs. input code single-ended unsigned single-ended signed differential mode 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 adc sample rate [ksps] inl [lsb] -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code inl [lsb]
177 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-39. dnl error vs. external v ref . t = 25 ? c, v cc = 3.6v, external reference . figure 37-40. dnl error vs. sample rate. t = 25 ? c, v cc = 3.6v, v ref = 3.0v external . single-ended unsigned single-ended signed differential mode 0.72 0.74 0.76 0.78 0.8 0.82 0.84 0.86 0.88 0.9 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 dnl [lsb] v [v] ref single-ended unsigned single-ended signed differential signed 0.79 0.8 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.9 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 adc sample rate [ksps] dnl [lsb]
178 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-41. dnl error vs. input code. figure 37-42. gain error vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code dnl [lsb] single-ended unsigned single-ended signed differential mode -4 -3 -2 -1 0 1 2 3 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 v gain error [mv] ref [v]
179 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-43. gain error vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . figure 37-44. offset error vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . single-ended unsigned single-ended signed differential mode -0.5 -0.2 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] gain error [mv] differential mode -2 -1.9 -1.8 -1.7 -1.6 -1.5 -1.4 -1.3 -1.2 -1.1 -1 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 offset error [mv] v ref [v]
180 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-45. gain error vs. temperature. v cc = 3.0v, v ref = external 2.0v . figure 37-46. offset error vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . single-ended unsigned single-ended signed differential signed -4 -3 -2 -1 0 1 2 3 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [oc] gain error [mv] differential signed -1.2 -1.1 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] offset error [mv]
181 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-47. noise vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . figure 37-48. noise vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . single-ended unsigned single-ended signed differential signed 0.4 0.55 0.7 0.85 1 1.15 1.3 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 v ref [v] noise [mv rms] single-ended unsigned single-ended signed differential signed 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] noise [mv rms]
182 xmega a4u [datasheet] 8387d?avr?02/2013 37.1.4 dac characteristics figure 37-49. dac inl error vs. v ref . v cc = 3.6v. figure 37-50. dnl error vs. v ref . t = 25 ? c, v cc = 3.6v. 25c 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 v ref [v] inl [lsb] 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 25oc 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1.6 1.8 2 2.2 2.4 2.6 2.8 3 dnl [lsb] v [v] ref
183 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-51. dac noise vs. temperature. v cc = 3.0v, v ref = 2.4v . 37.1.5 analog comparator characteristics figure 37-52. analog comparator hysteresis vs. v cc . high-speed, small hysteresis . 0.165 0.167 0.169 0.171 0.173 0.175 0.177 0.179 0.181 0.183 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [oc] noise [mv rms] 85 c 25 c -40 c 7 8 9 10 11 12 13 14 15 16 17 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv]
184 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-53. analog comparator hysteresis vs. v cc . low power, small hysteresis . figure 37-54. analog comparator hysteresis vs. v cc . high-speed mode, large hysteresis . 85 c 25 c -40 c 25 26 27 28 29 30 31 32 33 34 35 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv] 85 c 25 c -40 c 20 22 24 26 28 30 32 34 36 38 40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv]
185 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-55. analog comparator hysteresis vs. v cc . low power, large hysteresis . figure 37-56. analog comparator current source vs. calibration value. temperature = 25c. 85 c 25 c -40 c 50 53 56 59 62 65 68 71 74 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv] 3.3v 3.0v 2.7v 2.2v 1.8v 2 3 4 5 6 7 8 0123456789101112131415 calib[3..0] i [a]
186 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-57. analog comparator current source vs. calibration value. v cc = 3.0v. figure 37-58. voltage scaler inl vs. scalefac. t = 25 ? c, v cc = 3.0v . 85c 25c -40c 3.5 4 4.5 5 5.5 6 6.5 7 0123456789101112131415 calib[3..0] i [a] 25c -0.150 -0.125 -0.100 -0.075 -0.050 -0.025 0 0.025 0.050 0 10203040506070 scalefac inl [lsb]
187 xmega a4u [datasheet] 8387d?avr?02/2013 37.1.6 internal 1.0v reference characteristics figure 37-59. adc/dac internal 1. 0v reference vs. temperature. 37.1.7 bod characteristics figure 37-60. bod thresholds vs. temperature. bod level = 1.6v . 3.3v 3.0v 2.7v 1.8v 0.987 0.989 0.991 0.993 0.995 0.997 0.999 1.001 1.003 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 bandgap voltage [v] temperature [c] rising vcc falling vcc 1.603 1.606 1.609 1.612 1.615 1.618 1.621 1.624 1.627 1.630 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] v bot [v]
188 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-61. bod thresholds vs. temperature. bod level = 3.0v . 37.1.8 external reset characteristics figure 37-62. minimum reset pin pulse width vs. v cc . rising vcc falling vcc 2.97 2.98 2.99 3.00 3.01 3.02 3.03 3.04 3.05 3.06 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] v bot [v] 85 c 25 c -40 c 80 85 90 95 100 105 110 115 120 125 130 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] t rst [ns]
189 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-63. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 1.8v . figure 37-64. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.0v . 85c 25c -40c 0 10 20 30 40 50 60 70 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v reset [v] i reset [a] 85c 25c -40c 0 15 30 45 60 75 90 105 120 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 v reset [v] i reset [a]
190 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-65. reset pin pull-up resi stor current vs. reset pin voltage. v cc = 3.3v . figure 37-66. reset pin input threshold voltage vs. v cc. v ih - reset pin read as ?1? . 85c 25c -40c 0 15 30 45 60 75 90 105 120 135 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 v reset [v] i reset [a] 85c 25c -40c 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v threshold [v]
191 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-67. reset pin input threshold voltage vs. v cc. v il - reset pin read as ?0? . 37.1.9 power-on reset characteristics figure 37-68. power-on reset current consumption vs. v cc . bod level = 3.0v, enabled in continuous mode . 85c 25c -40c 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v threshold [v] 85 c 25 c -40 c 0 100 200 300 400 500 600 700 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 v cc [v] i cc [ua]
192 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-69. power-on reset current consumption vs. v cc . bod level = 3.0v, enabled in sampled mode . 37.1.10 oscillator characteristics 37.1.10.1 ultra low-power internal oscillator figure 37-70. ultra low-power internal oscillator frequency vs. temperature. 85 c 25 c -40 c 0 65 130 195 260 325 390 455 520 585 650 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 v cc [v] i cc [a] 3.3v 3.0v 2.7v 2.2v 1.8v 30.5 30.7 30.9 31.1 31.3 31.5 31.7 31.9 32.1 32.3 32.5 32.7 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 frequency [khz] temperature [c]
193 xmega a4u [datasheet] 8387d?avr?02/2013 37.1.10.2 32.768khz internal oscillator figure 37-71. 32.768khz internal osci llator frequency vs. temperature. figure 37-72. 32.768khz internal oscill ator frequency vs. calibration value. v cc = 3.0v, t = 25c . 3.3v 3.0v 2.7v 2.2v 1.8v 32.59 32.61 32.63 32.65 32.67 32.69 32.71 32.73 32.75 32.77 32.79 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 frequency [khz] temperature [c] 3.0 v 22 25 28 31 34 37 40 43 46 49 52 0 24 48 72 96 120 144 168 192 216 240 264 rc32kcal[7..0] frequency [khz]
194 xmega a4u [datasheet] 8387d?avr?02/2013 37.1.10.3 2mhz internal oscillator figure 37-73. 2mhz internal oscillator frequency vs. temperature. dfll disabled . figure 37-74. 2mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 1.98 2.00 2.02 2.04 2.06 2.08 2.10 2.12 2.14 2.16 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.3v 3.0v 2.7v 2.2v 1.8v 1.991 1.993 1.995 1.997 1.999 2.001 2.003 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz]
195 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-75. 2mhz internal oscillator cala calibration step size. v cc = 3v . 37.1.10.4 32mhz internal oscillator figure 37-76. 32mhz internal osci llator frequency vs. temperature. dfll disabled . 85c 25c -40c 0.15 0.17 0.19 0.21 0.23 0.25 0.27 0.29 0.31 0 102030405060708090100110120130 cala step size [%] 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 36.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v
196 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-77. 32mhz internal osci llator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . figure 37-78. 32mhz internal oscillator cala calibration step size. v cc = 3.0v . 3.3v 3.0v 2.7v 2.2v 1.8v 31.88 31.9 31.92 31.94 31.96 31.98 32 32.02 32.04 32.06 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz] 85c 25c -40c 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 0.32 0.34 0.36 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 cala step size [%]
197 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-79. 32mhz internal oscillator frequency vs. calb calibration value. v cc = 3.0v . 37.1.10.5 32mhz internal oscillator calibrated to 48mhz figure 37-80. 48mhz internal osci llator frequency vs. temperature. dfll disabled. 85c 25c -40c 25 30 35 40 45 50 55 60 65 70 75 0 7 14 21 28 35 42 49 56 63 calb frequency [mhz] 47 48 49 50 51 52 53 54 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v
198 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-81. 48mhz internal osci llator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . figure 37-82. 48mhz internal oscillator cala calibration step size. v cc = 3.0v . 47.70 47.75 47.80 47.85 47.90 47.95 48.00 48.05 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 85c 25c -40c 0.11 0.14 0.17 0.20 0.23 0.26 0.29 0.32 0.35 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 cala step size [%]
199 xmega a4u [datasheet] 8387d?avr?02/2013 37.1.11 two-wire interface characteristics figure 37-83. sda hold time vs. temperature. figure 37-84. sda hold time vs. supply voltage. 3 2 1 0 50 100 150 200 250 300 350 400 450 500 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] hold time [ns] 3 2 1 0 50 100 150 200 250 300 350 400 450 500 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] hold time [ns]
200 xmega a4u [datasheet] 8387d?avr?02/2013 37.1.12 pdi characteristics figure 37-85. maximum pdi frequency vs. v cc . 85 c 25 c -40 c 12 14 16 18 20 22 24 26 28 30 32 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] frequency max [mhz]
201 xmega a4u [datasheet] 8387d?avr?02/2013 37.2 atxmega32a4u 37.2.1 current consumption 37.2.1.1 active mode supply current figure 37-86. active supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 37-87. active supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . 3.6 v 3.0 v 2.7 v 2.2 v 1.8 v 1.6 v 0 100 200 300 400 500 600 700 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 i cc [a] frequency [mhz] 3.6 v 3.0 v 2.7 v 1.8 v 1.6 v 0 2 4 6 8 10 12 14 0 4 8 121620242832 i cc [ma] frequency [mhz] 2.2 v
202 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-88. active mode supply current vs. v cc . f sys = 32.768khz internal oscillator . figure 37-89. active mode supply current vs. v cc . f sys = 1mhz external clock . 85c 25c -40c 40 50 60 70 80 90 100 110 120 130 140 150 160 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ a] 85c 25c -40c 100 160 220 280 340 400 460 520 580 640 700 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ a]
203 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-90. active mode supply current vs. v cc . f sys = 2mhz internal oscillator . figure 37-91. active mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz. 85c 25c -40c 400 500 600 700 800 900 1000 1100 1200 1300 1400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ a] 85c 25c -40c 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ma]
204 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-92. active mode supply current vs. v cc . f sys = 32mhz internal oscillator. 37.2.1.2 idle mode supply current figure 37-93. idle mode supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . 85c 25c -40c 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] i cc [ma] 3.6 v 3.0 v 2.7 v 2.2 v 1.8 v 1.6 v 0 20 40 60 80 100 120 140 160 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 i cc [a] frequency [mhz]
205 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-94. idle mode supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . figure 37-95. idle mode supply current vs. v cc . f sys = 32.768khz internal oscillator . 3.6 v 3.0 v 2.7 v 1.8 v 1.6 v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 4 8 121620242832 i cc [ma] frequency [mhz] 2.2 v 85c 25c -40c 27.0 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 32.5 33.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
206 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-96. idle mode supply current vs. v cc . f sys = 1mhz external clock . figure 37-97. idle mode supply current vs. v cc . f sys = 2mhz internal oscillator . 85c 25c -40c 50 60 70 80 90 100 110 120 130 140 150 160 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] 85c 25c -40c 160 180 200 220 240 260 280 300 320 340 360 380 400 420 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a]
207 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-98. idle mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz . figure 37-99. idle mode current vs. v cc . f sys = 32mhz internal oscillator . 85c 25c -40c 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [ma] 85c 25c -40c 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] i cc [ma]
208 xmega a4u [datasheet] 8387d?avr?02/2013 37.2.1.3 power-down mode supply current figure 37-100. power-down mode supply current vs. temperature. all functions disabled . figure 37-101. power-down mode supply current vs. v cc . all functions disabled . 3.6 v 3.0 v 2.7 v 2.2 v 1.8 v 1.6 v 0.0 0.2 0.3 0.5 0.6 0.8 0.9 1.1 1.2 -45-35-25-15-5 5 1525354555657585 i cc [a] temperature [c] 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] i cc [a]
209 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-102. power-down mode supply current vs. v cc . watchdog and sampled bod enabled . 37.2.1.4 power-save mode supply current figure 37-103. power-save mode supply current vs.v cc . real time counter enabled and running from 1.024khz output of 32.768khz tosc. 85c 25c -40c 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] i cc [a] normal mode low-power mode 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
210 xmega a4u [datasheet] 8387d?avr?02/2013 37.2.1.5 standby mode supply current figure 37-104. standby supply current vs. v cc . standby, f sys =1mhz . figure 37-105. standby supply current vs. v cc . 25c, running from different crystal oscillators . 85c 25c -40c 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] i cc [a] 16mhz 12mhz 8mhz 2mhz 0.454mhz 160 200 240 280 320 360 400 440 480 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] i cc [a]
211 xmega a4u [datasheet] 8387d?avr?02/2013 37.2.2 i/o pin characteristics 37.2.2.1 pull-up figure 37-106. i/o pin pull-up resistor current vs. input voltage. v cc = 1.8v . figure 37-107. i/o pin pull-up resistor current vs. input voltage. v cc = 3.0v . 0 10 20 30 40 50 60 70 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 i pin [a] v pin [v] -40c 25c 85c 0 15 30 45 60 75 90 105 120 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 i pin [a] v pin [v] -40c 25c 85c
212 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-108. i/o pin pull-up resistor current vs. input voltage. v cc = 3.3v . 37.2.2.2 output voltage vs. sink/source current figure 37-109. i/o pin output voltage vs. source current. v cc = 1.8v . 0 15 30 45 60 75 90 105 120 135 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 i pin [a] v pin [v] -40c 25c 85c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 v pin [v] -40c 25c 85c i pin [ma]
213 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-110. i/o pin output voltage vs. source current. v cc = 3.0v . figure 37-111. i/o pin output voltage vs. source current. v cc = 3.3v . 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 v pin [v] i pin [ma] -40c 25c 85c 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 v pin [v] i pin [ma] -40c 25c 85c
214 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-112. i/o pin output voltage vs. source current. figure 37-113. i/o pin output voltage vs. sink current. v cc = 1.8v . 3.6 v 3.3 v 3.0 v 2.7 v 1.8 v 1.6 v 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 -24 -21 -18 -15 -12 -9 -6 -3 0 v pin [v] i pin [ma] 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 2 4 6 8 101214161820 v pin [v] i pin [ma] -40c 25c 85c
215 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-114. i/o pin output voltage vs. sink current. v cc = 3.0v . figure 37-115. i/o pin output voltage vs. sink current. v cc = 3.3v . 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 3 6 9 12 15 18 21 24 27 30 v pin [v] i pin [ma] -40c 25c 85c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 3 6 9 12 15 18 21 24 27 30 v pin [v] i pin [ma] -40c 25c 85c
216 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-116. i/o pin output voltage vs. sink current. 37.2.2.3 thresholds and hysteresis figure 37-117. i/o pin input threshold voltage vs. v cc. t = 25c . 3.6 v 3.3 v 3.0 v 2.7 v 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 0 3 6 9 12 15 18 21 24 27 30 v pin [v] i pin [ma] 1.6 v 1.8 v vil vih 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vthreshold [v]
217 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-118. i/o pin input threshold voltage vs. v cc . v ih i/o pin read as ?1? . figure 37-119. i/o pin input threshold voltage vs. v cc . v il i/o pin read as ?0? . 85 c 25 c -40 c 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vthreshold [v] 85 c 25 c -40 c 0.40 0.55 0.70 0.85 1.00 1.15 1.30 1.45 1.60 1.75 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vthreshold [v]
218 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-120. i/o pin input hysteresis vs. v cc . 37.2.3 adc characteristics figure 37-121. inl error vs. external v ref . t = 25 ? c, v cc = 3.6v, external reference . 85c 25c -40c 0.17 0.19 0.21 0.23 0.25 0.27 0.29 0.31 0.33 0.35 0.37 0.39 0.41 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vhysteresis [v] single-ended unsigned single-ended signed differential signed 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 v [v] inl [lsb] ref
219 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-122. inl error vs. sample rate. t = 25 ? c, v cc = 3.6v, v ref = 3.0v external . figure 37-123. inl error vs. input code single-ended unsigned single-ended signed differential mode 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 adc sample rate [ksps] inl [lsb] -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code inl [lsb]
220 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-124. dnl error vs. external v ref . t = 25 ? c, v cc = 3.6v, external reference . figure 37-125. dnl error vs. sample rate. t = 25 ? c, v cc = 3.6v, v ref = 3.0v external . single-ended unsigned single-ended signed differential mode 0.72 0.74 0.76 0.78 0.8 0.82 0.84 0.86 0.88 0.9 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 dnl [lsb] v [v] ref single-ended unsigned single-ended signed differential signed 0.79 0.8 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.9 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 adc sample rate [ksps] dnl [lsb]
221 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-126. dnl e rror vs. input code. figure 37-127. gain error vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code dnl [lsb] single-ended unsigned single-ended signed differential mode -4 -3 -2 -1 0 1 2 3 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 v gain error [mv] ref [v]
222 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-128. gain error vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . figure 37-129. offset error vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . single-ended unsigned single-ended signed differential mode -0.5 -0.2 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] gain error [mv] differential mode -2 -1.9 -1.8 -1.7 -1.6 -1.5 -1.4 -1.3 -1.2 -1.1 -1 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 offset error [mv] v ref [v]
223 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-130. gain error vs. temperature. v cc = 3.0v, v ref = external 2.0v . figure 37-131. offset error vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . single-ended unsigned single-ended signed differential signed -4 -3 -2 -1 0 1 2 3 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [oc] gain error [mv] differential signed -1.2 -1.1 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] offset error [mv]
224 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-132. noise vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . figure 37-133. noise vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . single-ended unsigned single-ended signed differential signed 0.4 0.55 0.7 0.85 1 1.15 1.3 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 v ref [v] noise [mv rms] single-ended unsigned single-ended signed differential signed 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] noise [mv rms]
225 xmega a4u [datasheet] 8387d?avr?02/2013 37.2.4 dac characteristics figure 37-134. dac inl error vs. v ref . v cc = 3.6v. figure 37-135. dnl error vs. v ref . t = 25 ? c, v cc = 3.6v. 25c 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 v ref [v] inl [lsb] 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 25oc 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1.6 1.8 2 2.2 2.4 2.6 2.8 3 dnl [lsb] v [v] ref
226 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-136. dac noise vs. temperature. v cc = 3.0v, v ref = 2.4v . 37.2.5 analog comparator characteristics figure 37-137. analog comparator hysteresis vs. v cc . high-speed, small hysteresis . 0.165 0.167 0.169 0.171 0.173 0.175 0.177 0.179 0.181 0.183 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [oc] noise [mv rms] 85 c 25 c -40 c 7 8 9 10 11 12 13 14 15 16 17 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv]
227 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-138. analog comparator hysteresis vs. v cc . low power, small hysteresis . figure 37-139. analog comparator hysteresis vs. v cc . high-speed mode, large hysteresis . 85 c 25 c -40 c 25 26 27 28 29 30 31 32 33 34 35 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv] 27 29 31 33 35 37 39 41 43 45 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v hyst [mv] v cc [v] 85c 25c -40c
228 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-140. analog comparator hysteresis vs. v cc . low power, large hysteresis . figure 37-141. analog comparator current source vs. calibration value. temperature = 25c. -40c 25c 85c 46 49 52 55 58 61 64 67 70 73 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v hyst [mv] v cc [v] 3.3v 3.0v 2.7v 2.2v 1.8v 2 3 4 5 6 7 8 0123456789101112131415 calib[3..0] i [a]
229 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-142. analog comparator current source vs. calibration value. v cc = 3.0v. figure 37-143. voltage scaler inl vs. scalefac. t = 25 ? c, v cc = 3.0v . 85c 25c -40c 3.5 4 4.5 5 5.5 6 6.5 7 0123456789101112131415 calib[3..0] i [a] 25c -0.150 -0.125 -0.100 -0.075 -0.050 -0.025 0 0.025 0.050 0 10203040506070 scalefac inl [lsb]
230 xmega a4u [datasheet] 8387d?avr?02/2013 37.2.6 internal 1.0v reference characteristics figure 37-144. adc/dac internal 1.0v reference vs. temperature. 37.2.7 bod characteristics figure 37-145. bod thresholds vs. temperature. bod level = 1.6v . 3.3v 3.0v 2.7v 1.8v 0.987 0.989 0.991 0.993 0.995 0.997 0.999 1.001 1.003 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 bandgap voltage [v] temperature [c] rising vcc falling vcc 1.603 1.606 1.609 1.612 1.615 1.618 1.621 1.624 1.627 1.630 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] v bot [v]
231 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-146. bod thresholds vs. temperature. bod level = 3.0v . 37.2.8 external reset characteristics figure 37-147. minimum reset pin pulse width vs. v cc . rising vcc falling vcc 2.97 2.98 2.99 3.00 3.01 3.02 3.03 3.04 3.05 3.06 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] v bot [v] 85 c 25 c -40 c 80 85 90 95 100 105 110 115 120 125 130 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] t rst [ns]
232 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-148. reset pin pull-up resistor current vs. reset pin voltage. v cc = 1.8v . figure 37-149. reset pin pull-up resistor current vs. reset pin voltage. v cc = 3.0v . 85c 25c -40c 0 10 20 30 40 50 60 70 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v reset [v] i reset [a] 85c 25c -40c 0 15 30 45 60 75 90 105 120 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 v reset [v] i reset [a]
233 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-150. reset pin pull-up resistor current vs. reset pin voltage. v cc = 3.3v . figure 37-151. reset pin input threshold voltage vs. v cc. v ih - reset pin read as ?1? . 85c 25c -40c 0 15 30 45 60 75 90 105 120 135 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 v reset [v] i reset [a] 85c 25c -40c 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v threshold [v]
234 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-152. reset pin input threshold voltage vs. v cc. v il - reset pin read as ?0? . 37.2.9 power-on reset characteristics figure 37-153. power-on reset current consumption vs. v cc . bod level = 3.0v, enabled in continuous mode . 85c 25c -40c 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc [v] v threshold [v] 85 c 25 c -40 c 0 100 200 300 400 500 600 700 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 v cc [v] i cc [ua]
235 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-154. power-on reset current consumption vs. v cc . bod level = 3.0v, enabled in sampled mode . 37.2.10 oscillator characteristics 37.2.10.1 ultra low-power internal oscillator figure 37-155. ultra low-power internal oscillator frequency vs. temperature. 85 c 25 c -40 c 0 65 130 195 260 325 390 455 520 585 650 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 v cc [v] i cc [a] 3.3v 3.0v 2.7v 2.2v 1.8v 30.5 30.7 30.9 31.1 31.3 31.5 31.7 31.9 32.1 32.3 32.5 32.7 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 frequency [khz] temperature [c]
236 xmega a4u [datasheet] 8387d?avr?02/2013 37.2.10.2 32.768khz internal oscillator figure 37-156. 32.768khz internal oscillator frequency vs. temperature. figure 37-157. 32.768khz internal osci llator frequency vs. calibration value. v cc = 3.0v, t = 25c . 3.3v 3.0v 2.7v 2.2v 1.8v 32.59 32.61 32.63 32.65 32.67 32.69 32.71 32.73 32.75 32.77 32.79 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 frequency [khz] temperature [c] 3.0 v 22 25 28 31 34 37 40 43 46 49 52 0 24 48 72 96 120 144 168 192 216 240 264 rc32kcal[7..0] frequency [khz]
237 xmega a4u [datasheet] 8387d?avr?02/2013 37.2.10.3 2mhz internal oscillator figure 37-158. 2mhz internal oscillator frequency vs. temperature. dfll disabled . figure 37-159. 2mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 1.98 2.00 2.02 2.04 2.06 2.08 2.10 2.12 2.14 2.16 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 3.3v 3.0v 2.7v 2.2v 1.8v 1.991 1.993 1.995 1.997 1.999 2.001 2.003 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz]
238 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-160. 2mhz internal oscillator cala calibration step size. v cc = 3v . 37.2.10.4 32mhz internal oscillator figure 37-161. 32mhz internal oscillator frequency vs. temperature. dfll disabled . 85c 25c -40c 0.15 0.17 0.19 0.21 0.23 0.25 0.27 0.29 0.31 0 102030405060708090100110120130 cala step size [%] 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 36.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v
239 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-162. 32mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . figure 37-163. 32mhz internal osci llator cala calibration step size. v cc = 3.0v . 3.3v 3.0v 2.7v 2.2v 1.8v 31.76 31.78 31.80 31.82 31.84 31.86 31.88 31.90 31.92 31.94 31.96 31.98 32.00 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] frequency [mhz] 85c 25c -40c 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 0.32 0.34 0.36 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 cala step size [%]
240 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-164. 32mhz internal oscillato r frequency vs. calb calibration value. v cc = 3.0v . 37.2.10.5 32mhz internal oscillator calibrated to 48mhz figure 37-165. 48mhz internal oscillator frequency vs. temperature. dfll disabled. 85c 25c -40c 25 30 35 40 45 50 55 60 65 70 75 0 7 14 21 28 35 42 49 56 63 calb frequency [mhz] 47 48 49 50 51 52 53 54 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v
241 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-166. 48mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . figure 37-167. 48mhz internal osci llator cala calibration step size. v cc = 3.0v . 47.70 47.75 47.80 47.85 47.90 47.95 48.00 48.05 -45-35-25-15-5 5 1525354555657585 temperature [c] frequency [mhz] 3.3v 3.0v 2.7v 2.2v 1.8v 85c 25c -40c 0.11 0.14 0.17 0.20 0.23 0.26 0.29 0.32 0.35 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 cala step size [%]
242 xmega a4u [datasheet] 8387d?avr?02/2013 37.2.11 two-wire interface characteristics figure 37-168. sda hold time vs. temperature. figure 37-169. sda hold time vs. supply voltage. 3 2 1 0 50 100 150 200 250 300 350 400 450 500 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] hold time [ns] 3 2 1 0 50 100 150 200 250 300 350 400 450 500 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] hold time [ns]
243 xmega a4u [datasheet] 8387d?avr?02/2013 37.2.12 pdi characteristics figure 37-170. maximum pdi frequency vs. v cc . 85 c 25 c -40 c 12 14 16 18 20 22 24 26 28 30 32 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] frequency max [mhz]
244 xmega a4u [datasheet] 8387d?avr?02/2013 37.3 atxmega64a4u 37.3.1 current consumption 37.3.1.1 active mode supply current figure 37-171. active supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 37-172. active supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . 3.6 v 3.0 v 2.7 v 2.2 v 1.8 v 1.6 v 0 100 200 300 400 500 600 700 0 0.10.20.30.40.50.60.70.80.9 1 i cc [a] frequency [mhz] 3.6 v 3.0 v 2.7 v 1.8 v 1.6 v 0 2 4 6 8 10 12 0 4 8 121620242832 i cc [ma] frequency [mhz] 2.2 v
245 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-173. active mode supply current vs. v cc . f sys = 32.768khz internal oscillator . figure 37-174. active mode supply current vs. v cc . f sys = 1mhz external clock . -40c 25c 85c 50 70 90 110 130 150 170 190 210 230 250 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 i cc [a] v cc [v] -40c 25c 85c 180 230 280 330 380 430 480 530 580 630 680 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 i cc [a] v cc [v]
246 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-175. active mode supply current vs. v cc . f sys = 2mhz internal oscillator . figure 37-176. active mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz. -40c 25c 85c 400 500 600 700 800 900 1000 1100 1200 1300 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 i cc [a] v cc [v] -40c 25c 85c 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 i cc [ma] v cc [v]
247 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-177. active mode supply current vs. v cc . f sys = 32mhz internal oscillator. 37.3.1.2 idle mode supply current figure 37-178. idle mode supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 i cc [ma] v cc [v] -40c 25c 85c 3.6 v 3.0 v 2.7 v 2.2 v 1.8 v 1.6 v 0 15 30 45 60 75 90 105 120 135 150 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 i cc [a] frequency [mhz]
248 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-179. idle mode supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . figure 37-180. idle mode supply current vs. v cc . f sys = 32.768khz internal oscillator . 3.6 v 3.0 v 2.7 v 1.8 v 1.6 v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 4 8 121620242832 i cc [ma] frequency [mhz] 2.2 v -40c 25c 85c 28.0 28.8 29.5 30.3 31.0 31.8 32.5 33.3 34.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 i cc [a] v cc [v]
249 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-181. idle mode supply current vs. v cc . f sys = 1mhz external clock . figure 37-182. idle mode supply current vs. v cc . f sys = 2mhz internal oscillator . 85c 25c -40c 45 57 69 81 93 105 117 129 141 153 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 i cc [a] v cc [v] -40c 25c 85c 150 175 200 225 250 275 300 325 350 375 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 i cc [a] v cc [v]
250 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-183. idle mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz . figure 37-184. idle mode current vs. v cc . f sys = 32mhz internal oscillator . -40c 25c 85c 0.65 0.80 0.95 11.0 12.5 14.0 15.5 17.0 18.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 i cc [ma] v cc [v] 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 i cc [ma] v cc [v] -40c 25c 85c
251 xmega a4u [datasheet] 8387d?avr?02/2013 37.3.1.3 power-down mode supply current figure 37-185. power-down mode supply current vs. temperature. all functions disabled . figure 37-186. power-down mode supply current vs. v cc . all functions disabled . 3.6 v 3.0 v 2.7 v 2.2 v 1.8 v 1.6 v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 i cc [a] temperature [c] -40c 25c 85c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 i cc [a] v cc [v]
252 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-187. power-down mode supply current vs. v cc . watchdog and sampled bod enabled . 37.3.1.4 power-save mode supply current figure 37-188. power-save mode supply current vs.v cc . real time counter enabled and running from 1.024khz output of 32.768khz tosc. 1.15 1.30 1.45 1.60 1.75 1.90 2.05 2.20 2.35 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 i cc [a] v cc [v] -40c 25c 85c normal mode low-power mode 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
253 xmega a4u [datasheet] 8387d?avr?02/2013 37.3.1.5 standby mode supply current figure 37-189. standby supply current vs. v cc . standby, f sys =1mhz . figure 37-190. standby supply current vs. v cc . 25c, running from different crystal oscillators . 85c 25c -40c 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] i cc [a] 16mhz 12mhz 8mhz 2mhz 0.454mhz 160 200 240 280 320 360 400 440 480 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] i cc [a]
254 xmega a4u [datasheet] 8387d?avr?02/2013 37.3.2 i/o pin characteristics 37.3.2.1 pull-up figure 37-191. i/o pin pull-up resistor current vs. input voltage. v cc = 1.8v . figure 37-192. i/o pin pull-up resistor current vs. input voltage. v cc = 3.0v . 0 10 20 30 40 50 60 70 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 i pin [a] v pin [v] -40c 25c 85c 0 15 30 45 60 75 90 105 120 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 i pin [a] v pin [v] -40c 25c 85c
255 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-193. i/o pin pull-up resistor current vs. input voltage. v cc = 3.3v . 37.3.2.2 output voltage vs. sink/source current figure 37-194. i/o pin output voltage vs. source current. v cc = 1.8v . 0 15 30 45 60 75 90 105 120 135 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 i pin [a] v pin [v] -40c 25c 85c 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 v pin [v] -40c 25c 85c i pin [ma]
256 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-195. i/o pin output voltage vs. source current. v cc = 3.0v . figure 37-196. i/o pin output voltage vs. source current. v cc = 3.3v . 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 v pin [v] i pin [ma] -40c 25c 85c 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 v pin [v] i pin [ma] -40c 25c 85c
257 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-197. i/o pin output voltage vs. source current. figure 37-198. i/o pin output voltage vs. sink current. v cc = 1.8v . 3.6 v 3.3 v 3.0 v 2.7 v 1.8 v 1.6 v 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 -24 -21 -18 -15 -12 -9 -6 -3 0 v pin [v] i pin [ma] 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 2 4 6 8 101214161820 v pin [v] i pin [ma] -40c 25c 85c
258 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-199. i/o pin output voltage vs. sink current. v cc = 3.0v . figure 37-200. i/o pin output voltage vs. sink current. v cc = 3.3v . 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 3 6 9 12 15 18 21 24 27 30 v pin [v] i pin [ma] -40c 25c 85c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 3 6 9 12 15 18 21 24 27 30 v pin [v] i pin [ma] -40c 25c 85c
259 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-201. i/o pin output voltage vs. sink current. 37.3.2.3 thresholds and hysteresis figure 37-202. i/o pin input threshold voltage vs. v cc. t = 25c . 3.6 v 3.3 v 3.0 v 2.7 v 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 0 3 6 9 12 15 18 21 24 27 30 v pin [v] i pin [ma] 1.6 v 1.8 v vil vih 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vthreshold [v]
260 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-203. i/o pin input threshold voltage vs. v cc . v ih i/o pin read as ?1? . figure 37-204. i/o pin input threshold voltage vs. v cc . v il i/o pin read as ?0? . 85 c 25 c -40 c 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vthreshold [v] 85 c 25 c -40 c 0.40 0.55 0.70 0.85 1.00 1.15 1.30 1.45 1.60 1.75 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vthreshold [v]
261 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-205. i/o pin input hysteresis vs. v cc . 37.3.3 adc characteristics figure 37-206. inl error vs. external v ref . t = 25 ? c, v cc = 3.6v, external reference . 85c 25c -40c 0.17 0.19 0.21 0.23 0.25 0.27 0.29 0.31 0.33 0.35 0.37 0.39 0.41 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vhysteresis [v] single-ended unsigned mode single-ended signed mode differential mode 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 inl [lsb] vref [v]
262 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-207. inl error vs. sample rate. t = 25 ? c, v cc = 2.7v, v ref = 1.0v external . figure 37-208. inl error vs. input code single-ended signed mode single-ended signed mode differential mode 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 inl [lsb] adc sample rate [ksps] 0 512 1024 1536 2048 2560 3072 3584 4096 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 inl [lsb] adc input code
263 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-209. dnl error vs. external v ref . t = 25 ? c, v cc = 3.6v, external reference . figure 37-210. dnl error vs. sample rate. t = 25 ? c, v cc = 2.7v, v ref = 1.0v external . single-ended unsigned mode single-ended signed mode dif f erential mode 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 dnl [lsb] vref [v] single-ended unsigned mode single-ended signed mode dif f erential mode 0.23 0.26 0.28 0.31 0.33 0.36 0.38 0.41 0.43 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 dnl [lsb] adc sample rate [ksps]
264 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-211. dnl error vs. input code. figure 37-212. gain error vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . 0 512 1024 1536 2048 2560 3072 3584 4096 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 dnl [lsb] adc input code single-ended unsigned mode single-ended signed mode dif f erential mode 0 2 4 6 8 10 12 1.01.21.41.61.82.02.22.42.62.83.0 gain error [mv] vref [v]
265 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-213. gain error vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . figure 37-214. offset error vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . single-ended unsigned mode single-ended signed mode dif f erential mode 0 1 2 3 4 5 6 7 1.61.82.02.22.42.62.83.03.23.43.6 gain erro r [mv] vcc [v] differential mode -1.5 -1.5 -1.4 -1.4 -1.3 -1.3 -1.2 -1.2 -1.1 -1.1 -1.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 offset error [mv] vref [v]
266 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-215. gain error vs. temperature. v cc = 2.7v, v ref = external 1.0v . figure 37-216. offset error vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . single-ended unsigned mode single-ended signed mode differential mode 0 1 2 3 4 5 6 7 -45-35-25-15-5 5 1525354555657585 gain error [mv] temperature [ o c] differential mode -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 offset error [mv] vcc [v]
267 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-217. noise vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . figure 37-218. noise vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . single-ended unsigend mode single-ended signed mode dif f erential mode 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 noise [mv rms] vref [v] single-ended unsigned mode single-ended signed mode dif f erential mode 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 no ise [mv rms] vcc [v]
268 xmega a4u [datasheet] 8387d?avr?02/2013 37.3.4 dac characteristics figure 37-219. dac inl error vs. v ref . v cc = 3.6v. figure 37-220. dnl error vs. v ref . v cc = 3.6v. 85c 25c -40c 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 dacinl [lsb] vref [v] 85c 25c -40c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 dac dnl [lsb] vref [v]
269 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-221. dac noise vs. temperature. v cc = 2.7v, v ref = 1.0v . 37.3.5 analog comparator characteristics figure 37-222. analog comparator hysteresis vs. v cc . high-speed, small hysteresis . 0.164 0.166 0.168 0.170 0.172 0.174 0.176 0.178 -45-35-25-15-5 5 1525354555657585 noise[mv rms] temperature [oc] 85c 25c -40c 15 16 17 18 19 20 21 22 23 24 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v hyst [mv] v cc [v]
270 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-223. analog comparator hysteresis vs. v cc . low power, small hysteresis . figure 37-224. analog comparator hysteresis vs. v cc . high-speed mode, large hysteresis . 85c 25c -40c 20 22 24 26 28 30 32 34 36 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v hyst [mv] v cc [v] 27 29 31 33 35 37 39 41 43 45 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v hyst [mv] v cc [v] 85c 25c -40c
271 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-225. analog comparator hysteresis vs. v cc . low power, large hysteresis . figure 37-226. analog comparator current source vs. calibration value. temperature = 25c. -40c 25c 85c 46 49 52 55 58 61 64 67 70 73 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v hyst [mv] v cc [v] 2 3 4 5 6 7 8 0123456789101112131415 i currentsource [a] currcaliba[3..0] 3.6v 3.0v 2.7v 2.2v 1.8v 1.6v
272 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-227. analog comparator current source vs. calibration value. v cc = 3.0v. figure 37-228. voltage scaler inl vs. scalefac. t = 25 ? c, v cc = 3.0v . 3.6 4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8 7.2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i currentsource [a] currcaliba[3..0] -40c 25c 85c -0.15 -0.12 -0.09 -0.06 -0.03 0.00 0.03 0.06 0.09 0.12 0.15 0 8 16 24 32 40 48 56 64 inl [lsb] scalefac
273 xmega a4u [datasheet] 8387d?avr?02/2013 37.3.6 internal 1.0v reference characteristics figure 37-229. adc/dac internal 1.0v reference vs. temperature. 37.3.7 bod characteristics figure 37-230. bod thresholds vs. temperature. bod level = 1.6v . 3.3 v 3.0 v 2.7 v 1.8 v 0.992 0.993 0.994 0.995 0.996 0.997 0.998 0.999 1.000 1.001 -45-35-25-15-5 5 1525354555657585 bandgap voltage [v] temperature [c] rising vcc falling vcc 1.617 1.620 1.623 1.626 1.629 1.632 1.635 1.638 1.641 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 v bot [v] temperature [c]
274 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-231. bod thresholds vs. temperature. bod level = 3.0v . 37.3.8 external reset characteristics figure 37-232. minimum reset pin pulse width vs. v cc . rising vcc falling vcc 3.00 3.01 3.02 3.03 3.04 3.05 3.06 3.07 -45-35-25-15-5 5 1525354555657585 v bot [v] temperature [c] -40c 25c 85c 85 90 95 100 105 110 115 120 125 130 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 t rst [ns] v cc [v]
275 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-233. reset pin pull-up resistor current vs. reset pin voltage. v cc = 1.8v . figure 37-234. reset pin pull-up resistor current vs. reset pin voltage. v cc = 3.0v . 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 i reset [a] v reset [v] -40c 25c 85c 0 15 30 45 60 75 90 105 120 135 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 i reset [a] v reset [v] -40c 25c 85c
276 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-235. reset pin pull-up resistor current vs. reset pin voltage. v cc = 3.3v . figure 37-236. reset pin input threshold voltage vs. v cc. v ih - reset pin read as ?1? . 0 15 30 45 60 75 90 105 120 135 150 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 i reset [a] v reset [ v] -40c 25c 85c 1.0 1.2 1.3 1.5 1.6 1.8 1.9 2.1 2.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v threshold [v] v cc [v] -40c 25c 85c
277 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-237. reset pin input threshold voltage vs. v cc. v il - reset pin read as ?0? . 37.3.9 power-on reset characteristics figure 37-238. power-on reset current consumption vs. v cc . bod level = 3.0v, enabled in continuous mode . -40c 25c 85c 0.40 0.55 0.70 0.85 1.00 1.15 1.30 1.45 1.60 1.75 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v threshold [v] v cc [v] -40c 25c 85c 0 50 100 150 200 250 300 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 i cc [a] v cc [v]
278 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-239. power-on reset current consumption vs. v cc . bod level = 3.0v, enabled in sampled mode . 37.3.10 oscillator characteristics 37.3.10.1 ultra low-power internal oscillator figure 37-240. ultra low-power internal oscillator frequency vs. temperature. 0 20 40 60 80 100 120 140 160 180 200 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 i cc [a] v cc [v] -40c 25c 85c 31.7 32.0 32.3 32.6 32.9 33.2 33.5 33.8 34.1 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 frequency [khz] temperature [c] 3.6v 3.0v 2.7v 2.2v 1.8v 1.6v
279 xmega a4u [datasheet] 8387d?avr?02/2013 37.3.10.2 32.768khz internal oscillator figure 37-241. 32.768khz internal oscillator frequency vs. temperature. figure 37-242. 32.768khz internal osci llator frequency vs. calibration value. v cc = 3.0v, t = 25c . 32.55 32.58 32.61 32.64 32.67 32.70 32.73 32.76 32.79 32.82 32.85 -45-35-25-15-5 5 1525354555657585 frequency [khz] temperature [c] 3.6v 3.0v 2.7v 2.2v 1.8v 1.6v 23 26 29 32 35 38 41 44 47 50 53 0 30 60 90 120 150 180 210 240 270 frequency [khz] rc32kcal[7..0]
280 xmega a4u [datasheet] 8387d?avr?02/2013 37.3.10.3 2mhz internal oscillator figure 37-243. 2mhz internal oscillator frequency vs. temperature. dfll disabled . figure 37-244. 2mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 1.96 1.98 2.00 2.02 2.04 2.06 2.08 2.10 2.12 -45-35-25-15-5 5 1525354555657585 frequency [mhz] temperature [c] 3.6v 3.0v 2.7v 2.2v 1.8v 1.6v 1.986 1.989 1.992 1.995 1.998 2.001 2.004 2.007 2.010 -45-35-25-15-5 5 1525354555657585 frequency [mhz] temperature [c] , 1.6v 1.8v 2.7v 3.0v 2.2v 3.6v
281 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-245. 2mhz internal oscillator cala calibration step size. v cc = 3v . 37.3.10.4 32mhz internal oscillator figure 37-246. 32mhz internal oscillator frequency vs. temperature. dfll disabled . 0.00 % 0.05 % 0.10 % 0.15 % 0.20 % 0.25 % 0.30 % 0 163248648096112128 frequency step size [%] cala -40c 25c 85c 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 -45-35-25-15-5 5 1525354555657585 frequency [mhz] temperature [c] 3.6v 3.0v 2.7v 2.2v 1.8v 1.6v
282 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-247. 32mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . figure 37-248. 32mhz internal osci llator cala calibration step size. v cc = 3.0v . 31.80 31.83 31.86 31.89 31.92 31.95 31.98 32.01 32.04 32.07 32.10 -45-35-25-15-5 5 1525354555657585 frequency [mhz] temperature [c] 3.6v 3.0v 2.7v 2.2v 1.8v 1.6v 0.10 % 0.13 % 0.15 % 0.18 % 0.20 % 0.23 % 0.25 % 0.28 % 0.30 % 0.33 % 0 15 30 45 60 75 90 105 120 135 frequency step size[%] cala -40c 85c 25c
283 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-249. 32mhz internal osci llator calb calibration step size. v cc = 3.0v 37.3.10.5 32mhz internal oscillator calibrated to 48mhz figure 37-250. 48mhz internal oscillator frequency vs. temperature. dfll disabled. 85c 25c -40c 0.80 % 1.00 % 1.20 % 1.40 % 1.60 % 1.80 % 2.00 % 2.20 % 2.40 % 2.60 % 2.80 % 0 8 16 24 32 40 48 56 64 frequency step size [%] calb 47.0 47.8 48.6 49.4 50.2 51.0 51.8 52.6 53.4 -45-35-25-15-5 5 1525354555657585 frequency[mhz] temperature [c] 3.6v 3.0v 2.7v 2.2v 1.8v 1.6v
284 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-251. 48mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . figure 37-252. 48mhz internal osci llator cala calibration step size. v cc = 3.0v 47.70 47.75 47.80 47.85 47.90 47.95 48.00 48.05 48.10 48.15 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 frequency[mhz] temperature [c] 3.6v 3.0v 2.7v 2.2v 1.8v 1.6v 85c 25c -40c 0.10 % 0.12 % 0.14 % 0.16 % 0.18 % 0.20 % 0.22 % 0.24 % 0.26 % 0.28 % 0.30 % 0 163248648096112128 frequency step size [%] cala
285 xmega a4u [datasheet] 8387d?avr?02/2013 37.3.11 two-wire interface characteristics figure 37-253. sda hold time vs. temperature. figure 37-254. sda hold time vs. supply voltage. 3 2 1 0 50 100 150 200 250 300 350 400 450 500 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] hold time [ns] 3 2 1 0 50 100 150 200 250 300 350 400 450 500 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] hold time [ns]
286 xmega a4u [datasheet] 8387d?avr?02/2013 37.3.12 pdi characteristics figure 37-255. maximum pdi frequency vs. v cc . -40c 25c 85c 10 13 15 18 20 23 25 28 30 33 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 frequency max [mhz] vcc [v]
287 xmega a4u [datasheet] 8387d?avr?02/2013 37.4 atxmega128a4u 37.4.1 current consumption 37.4.1.1 active mode supply current figure 37-256. active supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . figure 37-257. active supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . 3.6v 3.0v 2.7v 2.2v 1.8v 1.6v 0 100 200 300 400 500 600 700 800 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency [mhz] icc [a] 3.6v 3.0v 2.7v 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 0 4 8 121620242832 frequency [mhz] icc [ma] 2.2v 1.8v
288 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-258. active mode supply current vs. v cc . f sys = 32.768khz internal oscillator . figure 37-259. active mode supply current vs. v cc . f sys = 1mhz external clock . 85c 25c -40c 0 30 60 90 120 150 180 210 240 270 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] icc [a] 85c 25c -40c 0 100 200 300 400 500 600 700 800 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] icc [a]
289 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-260. active mode supply current vs. v cc . f sys = 2mhz internal oscillator . figure 37-261. active mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz. 85c 25c -40c 0 175 350 525 700 875 1050 1225 1400 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] icc [a] 85c 25c -40c 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2 5.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] icc [ma]
290 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-262. active mode supply current vs. v cc . f sys = 32mhz internal oscillator. 37.4.1.2 idle mode supply current figure 37-263. idle mode supply current vs. frequency. f sys = 0 - 1mhz external clock, t = 25c . 85c 25c -40c 7.0 7.8 8.6 9.4 10.2 11.0 11.8 12.6 13.4 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] icc [ma] 3.6 v 3.0 v 2.7 v 2.2 v 1.8 v 1.6 v 0 20 40 60 80 100 120 140 160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency [mhz] icc [a]
291 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-264. idle mode supply current vs. frequency. f sys = 1 - 32mhz external clock, t = 25c . figure 37-265. idle mode supply current vs. v cc . f sys = 32.768khz internal oscillator . 3.6v 3.0v 2.7v 0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 0 4 8 121620242832 frenquecy [mhz] icc [ma] 2.2v 1.8v 85c 25c -40c 27 28 29 30 31 32 33 34 35 36 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] icc [a]
292 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-266. idle mode supply current vs. v cc . f sys = 1mhz external clock . figure 37-267. idle mode supply current vs. v cc . f sys = 2mhz internal oscillator . 85c 25c -40c 50 60 70 80 90 100 110 120 130 140 150 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] icc [a] 85c 25c -40c 90 110 130 150 170 190 210 230 250 270 290 310 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] icc [a]
293 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-268. idle mode supply current vs. v cc . f sys = 32mhz internal oscillator prescaled to 8mhz . figure 37-269. idle mode current vs. v cc . f sys = 32mhz internal oscillator . 85 c 25 c -40 c 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] icc [ma] 85c 25c -40c 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 vcc [v] icc [ma]
294 xmega a4u [datasheet] 8387d?avr?02/2013 37.4.1.3 power-down mode supply current figure 37-270. power-down mode supply current vs. temperature. all functions disabled . figure 37-271. power-down mode supply current vs. v cc . all functions disabled . 3.6v 3.0v 2.7v 2.2v 1.8v 1.6v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -45-35-25-15-5 5 1525354555657585 temperature [c] icc [a] 85c 25c -40c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] icc [a]
295 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-272. power-down mode supply current vs. v cc . watchdog and sampled bod enabled . 37.4.1.4 power-save mode supply current figure 37-273. power-save mode supply current vs.v cc . real time counter enabled and running from 1.024khz output of 32.768khz tosc. 85c 25c -40c 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] icc [a] normal mode low-power mode 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 v cc [v] i cc [a] 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
296 xmega a4u [datasheet] 8387d?avr?02/2013 37.4.1.5 standby mode supply current figure 37-274. standby supply current vs. v cc . standby, f sys =1mhz . figure 37-275. standby supply current vs. v cc . 25c, running from different crystal oscillators . 85c 25c -40c 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] i cc [a] 16mhz 12mhz 8mhz 2mhz 0.454mhz 160 200 240 280 320 360 400 440 480 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] i cc [a]
297 xmega a4u [datasheet] 8387d?avr?02/2013 37.4.2 i/o pin characteristics 37.4.2.1 pull-up figure 37-276. i/o pin pull-up resistor current vs. input voltage. v cc = 1.8v . figure 37-277. i/o pin pull-up resistor current vs. input voltage. v cc = 3.0v . 85c 25c -40c 0 8 16 24 32 40 48 56 64 72 0.10.30.50.70.91.11.31.51.7 v pin [v] i [a] 85c 25c -40c 0 15 30 45 60 75 90 105 120 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 v pin [v] i [a]
298 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-278. i/o pin pull-up resistor current vs. input voltage. v cc = 3.3v . 37.4.2.2 output voltage vs. sink/source current figure 37-279. i/o pin output voltage vs. source current. v cc = 1.8v . 85 c 25 c -40 c 0 15 30 45 60 75 90 105 120 135 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4 v pin [v] i [a] 85c 25c -40c 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 -10-9-8-7-6-5-4-3-2-1 0 i pin [ma] v pin [v]
299 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-280. i/o pin output voltage vs. source current. v cc = 3.0v . figure 37-281. i/o pin output voltage vs. source current. v cc = 3.3v . 85c 25c -40c 0.5 0.85 1.2 1.55 1.9 2.25 2.6 2.95 3.3 -30-27-24-21-18-15-12 -9 -6 -3 0 i pin [ma] v pin [v] 85c 25c -40c 0.5 0.8 1.1 1.4 1.7 2 2.3 2.6 2.9 3.2 3.5 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 i pin [ma] v pin [v]
300 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-282. i/o pin output voltage vs. source current. figure 37-283. i/o pin output voltage vs. sink current. v cc = 1.8v . 3.6v 3.3v 3.0v 2.7v 1.8v 1.6v 0.5 0.85 1.2 1.55 1.9 2.25 2.6 2.95 3.3 3.65 -24 -21 -18 -15 -12 -9 -6 -3 0 i pin [ma] v pin [v] -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 2 4 6 8 10 12 14 16 18 20 i pin [ma] v pin [v] 85c 25c
301 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-284. i/o pin output voltage vs. sink current. v cc = 3.0v . figure 37-285. i/o pin output voltage vs. sink current. v cc = 3.3v . 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0 3 6 9 12 15 18 21 24 27 30 i pin [ma] v pin [v] 85c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 3 6 9 12 15 18 21 24 27 30 i pin [ma] v pin [v]
302 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-286. i/o pin output voltage vs. sink current. 37.4.2.3 thresholds and hysteresis figure 37-287. i/o pin input threshold voltage vs. v cc. t = 25c . 3.6v 3.3v 3.0v 2.7v 0 0.15 0.3 0.45 0.6 0.75 0.9 1.05 1.2 1.35 1.5 0 3 6 9 12 15 18 21 24 27 30 i pin [ma] v pin [v] 1.6v 1.8v vil vih 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vthreshold [v]
303 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-288. i/o pin input threshold voltage vs. v cc . v ih i/o pin read as ?1? . figure 37-289. i/o pin input threshold voltage vs. v cc . v il i/o pin read as ?0? . 85 c 25 c -40 c 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vthreshold [v] 85 c 25 c -40 c 0.40 0.55 0.70 0.85 1.00 1.15 1.30 1.45 1.60 1.75 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vthreshold [v]
304 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-290. i/o pin input hysteresis vs. v cc . 37.4.3 adc characteristics figure 37-291. inl error vs. external v ref . t = 25 ? c, v cc = 3.6v, external reference . 85c 25c -40c 0.17 0.19 0.21 0.23 0.25 0.27 0.29 0.31 0.33 0.35 0.37 0.39 0.41 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] vthreshold [v] single-ended unsigned single-ended signed differential signed 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 v [v] inl [lsb] ref
305 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-292. inl error vs. sample rate. t = 25 ? c, v cc = 3.6v, v ref = 3.0v external . figure 37-293. inl error vs. input code single-ended unsigned single-ended signed differential mode 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 adc sample rate [ksps] inl [lsb] -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code inl [lsb]
306 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-294. dnl error vs. external v ref . t = 25 ? c, v cc = 3.6v, external reference . figure 37-295. dnl error vs. sample rate. t = 25 ? c, v cc = 3.6v, v ref = 3.0v external . single-ended unsigned single-ended signed differential mode 0.72 0.74 0.76 0.78 0.8 0.82 0.84 0.86 0.88 0.9 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 dnl [lsb] v [v] ref single-ended unsigned single-ended signed differential signed 0.79 0.8 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.9 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 adc sample rate [ksps] dnl [lsb]
307 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-296. dnl e rror vs. input code. figure 37-297. gain error vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 0 512 1024 1536 2048 2560 3072 3584 4096 adc input code dnl [lsb] single-ended unsigned single-ended signed differential mode -4 -3 -2 -1 0 1 2 3 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 v gain error [mv] ref [v]
308 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-298. gain error vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . figure 37-299. offset error vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . single-ended unsigned single-ended signed differential mode -0.5 -0.2 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] gain error [mv] differential mode -2 -1.9 -1.8 -1.7 -1.6 -1.5 -1.4 -1.3 -1.2 -1.1 -1 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 offset error [mv] v ref [v]
309 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-300. gain error vs. temperature. v cc = 3.0v, v ref = external 2.0v . figure 37-301. offset error vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . single-ended unsigned single-ended signed differential signed -4 -3 -2 -1 0 1 2 3 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [oc] gain error [mv] differential signed -1.2 -1.1 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] offset error [mv]
310 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-302. noise vs. v ref . t = 25 ? c, v cc = 3.6v, adc sampling speed = 500ksps . figure 37-303. noise vs. v cc . t = 25 ? c, v ref = external 1.0v, adc sampling speed = 500ksps . single-ended unsigned single-ended signed differential signed 0.4 0.55 0.7 0.85 1 1.15 1.3 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 v ref [v] noise [mv rms] single-ended unsigned single-ended signed differential signed 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] noise [mv rms]
311 xmega a4u [datasheet] 8387d?avr?02/2013 37.4.4 dac characteristics figure 37-304. dac inl error vs. v ref . v cc = 3.6v. figure 37-305. dnl error vs. v ref . t = 25 ? c, v cc = 3.6v. 25c 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 v ref [v] inl [lsb] 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 25oc 0.6 0.65 0.7 0.75 0.8 0.85 0.9 1.6 1.8 2 2.2 2.4 2.6 2.8 3 dnl [lsb] v [v] ref
312 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-306. dac noise vs. temperature. v cc = 3.0v, v ref = 2.4v . 37.4.5 analog comparator characteristics figure 37-307. analog comparator hysteresis vs. v cc . high-speed, small hysteresis . 0.165 0.167 0.169 0.171 0.173 0.175 0.177 0.179 0.181 0.183 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [oc] noise [mv rms] -40c 25c 85c 4 5 6 7 8 9 10 11 12 13 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv]
313 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-308. analog comparator hysteresis vs. v cc . low power, small hysteresis . figure 37-309. analog comparator hysteresis vs. v cc . high-speed mode, large hysteresis . -40c 25c 85c 15 16 17 18 19 20 21 22 23 24 25 26 27 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv] -40c 25c 85c 14 16 18 20 22 24 26 28 30 32 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv]
314 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-310. analog comparator hysteresis vs. v cc . low power, large hysteresis . figure 37-311. analog comparator current source vs. calibration value. temperature = 25c. 32 36 40 44 48 52 56 60 64 68 -40c 25c 85c 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v hyst [mv] 3.6v 3.0v 2.2v 1.8v 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 0123456789101112131415 currcaliba[3..0] i currentsource [a]
315 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-312. analog comparator current source vs. calibration value. v cc = 3.0v. figure 37-313. voltage scaler inl vs. scalefac. t = 25 ? c, v cc = 3.0v . 85c 25c -40c 3 3.5 4 4.5 5 5.5 6 6.5 7 0123456789101112131415 currcaliba[3..0] i currentsource [a] 25c -0.150 -0.125 -0.100 -0.075 -0.050 -0.025 0 0.025 0.050 0 10203040506070 scalefac inl [lsb]
316 xmega a4u [datasheet] 8387d?avr?02/2013 37.4.6 internal 1.0v reference characteristics figure 37-314. adc/dac internal 1.0v reference vs. temperature. 37.4.7 bod characteristics figure 37-315. bod thresholds vs. temperature. bod level = 1.6v . 3.6v 3.0v 2.7v 1.8v 1.6v 0.9984 0.9988 0.9992 0.9996 1 1.0004 1.0008 1.0012 1.0016 1.002 1.0024 -40-30-20-10 0 1020304050607080 temperature [c] bandgap voltage [v] rising vcc falling vcc 1.584 1.587 1.59 1.593 1.596 1.599 1.602 1.605 1.608 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 temperature [c] v bot [v]
317 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-316. bod thresholds vs. temperature. bod level = 3.0v . 37.4.8 external reset characteristics figure 37-317. minimum reset pin pulse width vs. v cc . rising vcc falling vcc 2.94 2.95 2.96 2.97 2.98 2.99 3 3.01 3.02 3.03 -45-35-25-15-5 5 1525354555657585 temperature [c] v bot [v] 85c 25c -40c 80 85 90 95 100 105 110 115 120 125 130 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vcc [v] t [ns] rst
318 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-318. reset pin pull-up resistor current vs. reset pin voltage. v cc = 1.8v . figure 37-319. reset pin pull-up resistor current vs. reset pin voltage. v cc = 3.0v . 0 8 16 24 32 40 48 56 64 72 80 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 85c 25c -40c v reset [v] i reset [a] 0 15 30 45 60 75 90 105 120 135 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 85c 25c -40c v reset [v] i reset [a]
319 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-320. reset pin pull-up resistor current vs. reset pin voltage. v cc = 3.3v . figure 37-321. reset pin input threshold voltage vs. v cc. v ih - reset pin read as ?1? . 85c 25c -40c 0 15 30 45 60 75 90 105 120 135 150 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 v reset [v] i reset [a] 85c 25c -40c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v threshold [v]
320 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-322. reset pin input threshold voltage vs. v cc. v il - reset pin read as ?0? . 37.4.9 power-on reset characteristics figure 37-323. power-on reset current consumption vs. v cc . bod level = 3.0v, enabled in continuous mode . 85c 25c -40c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v cc [v] v threshold [v] 85 c 25 c -40 c 0 100 200 300 400 500 600 700 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 v cc [v] i cc [ua]
321 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-324. power-on reset current consumption vs. v cc . bod level = 3.0v, enabled in sampled mode . 37.4.10 oscillator characteristics 37.4.10.1 ultra low-power internal oscillator figure 37-325. ultra low-power internal oscillator frequency vs. temperature. 85 c 25 c -40 c 0 65 130 195 260 325 390 455 520 585 650 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 v cc [v] i cc [a] 3.6v 3.3v 3.0v 2.7v 1.8v 1.6v 31.50 31.75 32.00 32.25 32.50 32.75 33.00 33.25 33.50 33.75 -40-30-20-100 1020304050607080 temperature [c] frequency [khz]
322 xmega a4u [datasheet] 8387d?avr?02/2013 37.4.10.2 32.768khz internal oscillator figure 37-326. 32.768khz internal oscillator frequency vs. temperature. figure 37-327. 32.768khz internal osci llator frequency vs. calibration value. v cc = 3.0v, t = 25c . 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 32.49 32.52 32.55 32.58 32.61 32.64 32.67 32.7 32.73 32.76 -40-30-20-10 0 1020304050607080 frequency [khz] 3.0 v 22 25 28 31 34 37 40 43 46 49 52 0 24 48 72 96 120 144 168 192 216 240 264 rc32kcal[7..0] frequency [khz]
323 xmega a4u [datasheet] 8387d?avr?02/2013 37.4.10.3 2mhz internal oscillator figure 37-328. 2mhz internal oscillator frequency vs. temperature. dfll disabled . figure 37-329. 2mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 1.98 2.00 2.02 2.04 2.06 2.08 2.10 2.12 2.14 2.16 -40-30-20-10 0 1020304050607080 temperature [c] frequency [mhz] 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 1.982 1.984 1.986 1.988 1.99 1.992 1.994 1.996 1.998 2 2.002 -40-30-20-10 0 1020304050607080 temperature [c] frequency [mhz]
324 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-330. 2mhz internal oscillator cala calibration step size. v cc = 3v . 37.4.10.4 32mhz internal oscillator figure 37-331. 32mhz internal oscillator frequency vs. temperature. dfll disabled . 85c 25c -40c 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 0 102030405060708090100110120130 cala step size [%] 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 31.5 31.95 32.4 32.85 33.3 33.75 34.2 34.65 35.1 35.55 36 -40-30-20-10 0 1020304050607080 temperature [c] frequency [mhz]
325 xmega a4u [datasheet] 8387d?avr?02/2013 figure 37-332. 32mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . figure 37-333. 32mhz internal osci llator cala calibration step size. v cc = 3.0v . 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 31.65 31.68 31.71 31.74 31.77 31.8 31.83 31.86 31.89 31.92 31.95 31.98 32.01 -40-30-20-10 0 1020304050607080 temperature [c] frequency [mhz] 85c 25c -40c 0 0.07 0.14 0.21 0.28 0.35 0.42 0.49 0.56 0.63 0.7 0 102030405060708090100110120130 cala step size [%]
326 xmega a4u [datasheet] 8387d?avr?02/2013 37.4.10.5 32mhz internal oscillator calibrated to 48mhz figure 37-334. 48mhz internal oscillator frequency vs. temperature. dfll disabled. figure 37-335. 48mhz internal oscillator frequency vs. temperature. dfll enabled, from the 32.768khz internal oscillator . 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 46.9 47.6 48.3 49 49.7 50.4 51.1 51.8 52.5 53.2 53.9 -40-30-20-10 0 1020304050607080 temperature [c] frequency [mhz] 3.6v 3.3v 3.0v 2.7v 2.2v 1.8v 47.55 47.6 47.65 47.7 47.75 47.8 47.85 47.9 47.95 48 -40-30-20-10 0 1020304050607080 temperature [c] frequency [mhz]
327 xmega a4u [datasheet] 8387d?avr?02/2013 37.4.11 two-wire interface characteristics figure 37-336. sda hold time vs. temperature. figure 37-337. sda hold time vs. supply voltage. 3 2 1 0 50 100 150 200 250 300 350 400 450 500 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature [c] hold time [ns] 3 2 1 0 50 100 150 200 250 300 350 400 450 500 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v cc [v] hold time [ns]
328 xmega a4u [datasheet] 8387d?avr?02/2013 37.4.12 pdi characteristics figure 37-338. maximum pdi frequency vs. v cc . -40c 25c 85c 10 13 15 18 20 23 25 28 30 33 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 frequency max [mhz] vcc [v] maximum pdi speed vs vcc
329 xmega a4u [datasheet] 8387d?avr?02/2013 38. errata 38.1 atxmega16a4u 38.1.1 rev. e ? adc may have missing codes in se unsigned mode at low temp and low vcc ? crc fails for range crc when end address is the last word address of a flash section ? awex fault protection restore is not done correct in pattern generation mode 1. adc may have missing codes in se unsi gned mode at low temp and low vcc the adc may have missing codes i single ended (se) unsigned mode below 0c when vcc is below 1.8v. problem fix/workaround use the adc in se signed mode. 2. crc fails for range crc when end address is the last word address of a flash section if boot read lock is enabled, the range crc cannot end on the last address of the application section. if application table read lock is enabled, the range crc cannot end on the last address before the application table. problem fix/workaround ensure that the end address used in range crc does not end at the last address before a section with read lock enabled. instead, use the dedicated crc commands for complete applic ations sections. 3. awex fault protection restore is not done correct in pattern generation mode when a fault is detected the outoven register is cleared, and when fault condition is cleared, outoven is restored according to the corresponding enabled dti channels. for co mmon waveform channel mode (cwcm), this has no effect as the outoven is correct after restoring from fault. fo r pattern generation mode (p gm), outoven should instead have been restored according to the dtlsbuf register. problem fix/workaround for cwcm no workaround is required. for pgm in latched mode, disable the dti channels before re turning from the fault conditio n. then, set correct outoven value and enable the dti channels, before the direction (dir) register is written to enable the correct outputs again. 38.1.2 rev. a - d not sampled.
330 xmega a4u [datasheet] 8387d?avr?02/2013 38.2 atxmega32a4u 38.2.1 rev. e ? adc may have missing codes in se unsigned mode at low temp and low vcc ? crc fails for range crc when end address is the last word address of a flash section ? awex fault protection restore is not done correct in pattern generation mode 1. adc may have missing codes in se unsi gned mode at low temp and low vcc the adc may have missing codes i single ended (se) unsigned mode below 0c when vcc is below 1.8v. problem fix/workaround use the adc in se signed mode. 2. crc fails for range crc when end address is the last word address of a flash section if boot read lock is enabled, the range crc cannot end on the last address of the application section. if application table read lock is enabled, the range crc cannot end on the last address before the application table. problem fix/workaround ensure that the end address used in range crc does not end at the last address before a section with read lock enabled. instead, use the dedicated crc commands for complete applic ations sections. 3. awex fault protection restore is not done correct in pattern generation mode when a fault is detected the outoven register is cleared, and when fault condition is cleared, outoven is restored according to the corresponding enabled dti channels. for co mmon waveform channel mode (cwcm), this has no effect as the outoven is correct after restoring from fault. fo r pattern generation mode (p gm), outoven should instead have been restored according to the dtlsbuf register. problem fix/workaround for cwcm no workaround is required. for pgm in latched mode, disable the dti channels before re turning from the fault conditio n. then, set correct outoven value and enable the dti channels, before the direction (dir) register is written to enable the correct outputs again. 38.2.2 rev. a - d not sampled.
331 xmega a4u [datasheet] 8387d?avr?02/2013 38.3 atxmega64a4u 38.3.1 rev. a ? adc may have missing codes in se unsi gned mode at low temp and low vcc 1. adc may have missing codes in se unsi gned mode at low temp and low vcc the adc may have missing codes i single ended (se) unsigned mode below 0c when vcc is below 1.8v. problem fix/workaround use the adc in se signed mode. 38.4 atxmega128a4u 38.4.1 rev. a ? adc may have missing codes in se unsi gned mode at low temp and low vcc 1. adc may have missing codes in se unsi gned mode at low temp and low vcc the adc may have missing codes i single ended (se) unsigned mode below 0c when vcc is below 1.8v. problem fix/workaround use the adc in se signed mode.
332 xmega a4u [datasheet] 8387d?avr?02/2013 39. datasheet revision history please note that the referring page numbers in this section ar e referred to this document. the referring revision in this section are referring to the document revision. 39.1 8387d ? 02/2013 1. updated typos in ?ordering information? on page 2 . 2. updated pe2 and pe3 pins in ?pinout/block diagram? on page 3 to indicate that these can be used as tosc pins. 3. renamed pin 19 from vdd to vcc in figure 2-1 on page 3 . 4. updated page size for atxmega128a4u in table 7-1 on page 16 . 5. added column for twi using external driver interface in table 32-3 on page 58 . 6. updated atxmega16a4u leakage current in table 36-7 on page 76 . 7. added application erase time for atxmega16a4u in table 36-21 on page 83 . 8. updated limits for vih and vil: atxmega16a4u: table 36-7 on page 76 atxmega32a4u: table 36-39 on page 97 atxmega64a4u: table 36-71 on page 119 atxmega128a4u: table 36-103 on page 141 9. updated dac clock and timing characteristics: atxmega16a4u: table 36-13 on page 79 . atxmega32a4u: table 36-45 on page 100 . atxmega64a4u: table 36-77 on page 122 . atxmega128a4u: table 36-109 on page 144 . 10. updated atxmega16a4u ?external clock characteristics? on page 85 . 11. added esr parameter to the external 16mhz cr ystal oscillator and xosc characteristics: atxmega16a4u: table 36-29 on page 86 . atxmega32a4u: table 36-61 on page 107 . atxmega64a4u: table 36-93 on page 129 . atxmega128a4u: table 36-125 on page 151 . 12. updated atxmega32a4u leakage current in table 36-39 on page 97 . 13. added application erase time for atxmega32a4u in table 36-53 on page 104 . 14. updated atxmega32a4u ?external clock characteristics? on page 106 . 15. updated atxmega32a4u current consumption in typical char acteristics section, see ?current consumption? on page 201 . 16. updated electrical characteristics for ?atxmega64a4u? on page 114 . 17. updated typical characteristics for ?atxmega64a4u? on page 244 . 18. added application erase time for atxmega128a4u in table 36-117 on page 148 . 19. updated atxmega128a4u ?external clock characteristics? on page 150 .
333 xmega a4u [datasheet] 8387d?avr?02/2013 39.2 8387c ? 03/2012 39.3 8387b ? 12/2011 1. updated ?ordering information? on page 2 . added a new package pw. 2. updated ?packaging information? on page 67 . a new package pw added. 3. updated the table 36-4 on page 73 with new values for i cc active power consumption. 4. updated all typical characteristics in ?active mode supply current? on page 158 . 5. updated all typical characteristics in ?power-down mode supply current? on page 165 . 6. added electrical characteristics for ?atxmega32a4u? on page 92 . 7. added electrical characteristics for ?atxmega64a4u? on page 114 . 8. added electrical characteristics for ?atxmega128a4u? on page 136 . 9. added typical characteristics for ?atxmega32a4u? on page 201 10. added typical characteristics for ?atxmega64a4u? on page 244 . 12. added typical characteristics for ?atxmega128a4u? on page 287 . 13. updated ?errata? on page 329 . 14. used atmel new datasheet template that includes atmel new addresses on the last page. 1. updated figure 2-1 on page 3 : ?block diagram and qfn/tqfp pinout? 2. updated figure 3-1 on page 6 : ?xmega a4u block diagram? 3. updated ?overview? on page 12 . 4. updated ?adc ? 12-bit analog to digital converter? on page 48 . 5. updated figure 28-1 on page 49 : ?adc overview.? 6. updated ?instruction set summary? on page 62 . 7. updated ?electrical characteristics? on page 71 . 8. updated ?typical characteristics? on page 158 . 9. the order of several figures in the chapter ?typical characteristics? has been changed 10. several new figures have been added to and some figures have been romoved from chapter ?typical characteristics? 11. several minor changes/corrections in te xt and figures have been performed 12. table 32-2 on page 59 has been corrected 13. table 32-4 on page 60 has been corrected 14. table 36-29 on page 85 has been corrected 15. table 36-30 on page 86 has been corrected 16. the heading ?i/o pin characteristics? on page 164 has been corrected (the text ?and reset? has been removed)
334 xmega a4u [datasheet] 8387d?avr?02/2013 39.4 8387a ? 07/2011 1. initial revision.
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339 xmega a4u [datasheet] 8387d?avr?02/2013
340 xmega a4u [datasheet] 8387d?avr?02/2013
i xmega a4u [datasheet] 8387d?avr?02/2013 table of contents 1. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. pinout/block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6. avr cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.4 alu - arithmetic logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.5 program flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.6 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.7 stack and stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.8 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.3 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.4 fuses and lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.7 i/o memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.8 data memory and bus arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.9 memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.10 device id and revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.11 i/o memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.12 flash and eeprom page size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. dmac ? direct memory access controller . . . . . . . . . . . . . . . . . . . 18 8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9. event system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10. system clock and clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.3 clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11. power management and sleep modes . . . . . . . . . . . . . . . . . . . . . . 23 11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ii xmega a4u [datasheet] 8387d?avr?02/2013 11.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.3 sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12. system control and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.3 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.4 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13. wdt ? watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14. interrupts and programmable multilevel interrupt controller . . . . . . 28 14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.3 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 15. i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 15.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 15.3 output driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 15.4 input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15.5 alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 16. tc0/1 ? 16-bit timer/counter type 0 and 1 . . . . . . . . . . . . . . . . . . 34 16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 16.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 17. tc2 - timer/counter type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 18. awex ? advanced waveform extension . . . . . . . . . . . . . . . . . . . . . 37 18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 19. hi-res ? high resolution extension . . . . . . . . . . . . . . . . . . . . . . . . 38 19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 19.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 20. rtc ? 16-bit real-time counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 20.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 21. usb ? universal serial bus interface . . . . . . . . . . . . . . . . . . . . . . . 40 21.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 21.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 22. twi ? two-wire interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 22.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 22.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 23. spi ? serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
iii xmega a4u [datasheet] 8387d?avr?02/2013 23.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 23.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 24. usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 24.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 24.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 25. ircom ? ir communication module . . . . . . . . . . . . . . . . . . . . . . . . 45 25.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 25.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 26. aes and des crypto engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 26.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 26.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 27. crc ? cyclic redundancy check generator . . . . . . . . . . . . . . . . . 47 27.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 27.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 28. adc ? 12-bit analog to digital converter . . . . . . . . . . . . . . . . . . . . 48 28.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 28.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 29. dac ? 12-bit digital to analog converter . . . . . . . . . . . . . . . . . . . . 50 29.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 29.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 30. ac ? analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 30.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 30.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 31. programming and debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 31.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 31.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 32. pinout and pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 32.1 alternate pin function descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 32.2 alternate pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 33. peripheral module address map . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 34. instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 35. packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 35.1 44a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 35.2 pw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 35.3 44m1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 35.4 49c2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 36. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 36.1 atxmega16a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 36.2 atxmega32a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 36.3 atxmega64a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 36.4 atxmega128a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
iv xmega a4u [datasheet] 8387d?avr?02/2013 37. typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 37.1 atxmega16a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 37.2 atxmega32a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 37.3 atxmega64a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 37.4 atxmega128a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 38. errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 38.1 atxmega16a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 38.2 atxmega32a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 38.3 atxmega64a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 38.4 atxmega128a4u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 39. datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 39.1 8387d ? 02/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 39.2 8387c ? 03/2012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 39.3 8387b ? 12/2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 39.4 8387a ? 07/2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong roa kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 8387d?avr?02/2013 disclaimer: the information in this document is provided in co nnection with atmel products. no lic ense, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. exc ept as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not li mited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any d irect, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the us e or inability to use this document, even if at mel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update th e information contained herein. un less specifically provided oth erwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications intend ed to support or sustain life. atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , avr ? , xmega ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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